Top Tech Jobs & Startup Jobs

Design and verify RF integrated circuits using SOI and RF CMOS processes. Perform RF device modeling, analog/RF circuit design, EM simulation, AMS verification, and Cadence-based layout including LVS/DRC/xRC.

Lead memory layout design from floor-planning to tapeout for advanced CMOS nodes. Apply process rules and verification (LVS/DRC/ERC), manage schedules, mentor juniors, automate layout flows, and document methodologies to meet quality and timing requirements.

Own the vision, strategy, and roadmap for AI-powered network observability products. Collaborate with engineering, design, data science, and GTM teams to integrate ML models for anomaly detection, root cause analysis, and predictive analytics. Drive product lifecycle from concept to launch, define KPIs, engage customers for feedback, and ensure successful SaaS/cloud-based deliveries.

Perform DFT tasks including MBIST and scan insertion, ATPG and pattern simulation, ATE pattern development and silicon debugging, yield analysis, and cross-functional DFT collaboration during design and silicon bring-up.

Design, build, test, and debug mainframe security and compliance software on z/OS using IBM Assembler (HLASM). Collaborate in Agile with product teams, automate tasks, modernize enterprise mainframe solutions, and support/debug production systems.

The role involves designing flip-chip-BGA packages for ASICs, collaborating on designs, managing projects, and improving processes.

Perform block- and full-chip static (IR) and dynamic (IVD) sign-off; power estimation (vector and vectorless); signal and power EM sign-off; implement custom power grids; conduct system-level PDN analysis across board, package, interposer, and die; collaborate with SoC and packaging teams on bump assignment and package routing optimization; run vectorless, vector, and mixed-mode dynamic analyses and PG grid resistance checks.

Lead development, optimization, and transfer of wafer fabrication processes (thin-film deposition, wafer thinning, thermal processes, implantation) to meet yield, quality, cost, and reliability targets. Drive yield improvement, defect reduction, DOE/SPC experiments, root-cause analysis, and process transfer to high-volume manufacturing. Collaborate cross-functionally, mentor junior staff, and manage supplier process and material improvements.

Lead development, optimization, and transfer of wafer fab processes (thin film, wafer thinning, thermal). Drive yield improvement and defect reduction using SPC/DOE/FMEA, perform root-cause analysis and corrective actions, define control plans and OCAP, support NPI and high-volume transfer, collaborate cross-functionally, mentor junior staff, and interface with suppliers.

Senior mainframe technical consultant delivering Broadcom mainframe software adoption: presentations, demos, installations, configurations, deployments and POCs. Architect solutions with sales teams, provide technical leadership during trials, document requirements, and build customer relationships. Travel-intensive role supporting multi-country accounts and meeting financial and internal process targets.