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The CPU Physical Design Engineer will implement custom CPU designs, conduct physical design flow, optimize designs, and collaborate on verification processes. They will work with EDA vendors and enhance methodologies for CPU design.

Develop and sustain integrated defect monitors for semiconductor processes. Own multiple monitors, analyze data statistically (e.g., JMP), troubleshoot complex issues, optimize tool performance and recipes, and lead continuous improvement to improve yields and prevent defect recurrence.

Develop and prototype software and modeling solutions for factory automation. Perform discrete event simulation, statistical analysis, and modeling to solve manufacturing and stochastic systems problems. Collaborate with cross-functional teams and industry partners to validate ideas and drive manufacturing roadmap improvements.

Design and implement CPU RTL for integer, floating point, and reservation station logic. Drive RTL coding, simulation, and optimization for power, performance, area, and timing. Participate in architecture definition, review verification plans, resolve RTL test failures, and provide technical leadership and cross-team collaboration to deliver CPU IP for full-chip integration.

Lead front-end RTL methodology for CPU design, leveraging AI tools to improve RTL coding, debug, and logic optimization. Drive methodology and architectural discussions, collaborate with architecture and backend teams, and deliver CPU IP meeting power, performance, area, and timing goals. Provide technical leadership and build a high-performing team.

Lead standardization and governance of product-level rebate accruals and TPT FIFO processes; drive automation/AI enhancements to accrual algorithms and tooling; maintain exception and override governance; support SOX controls, audit readiness, UAT and cutover activities; build financial models and enable stakeholders with templates, reporting, and training to ensure scalable, auditable rebate execution and Vistex/V4 adoption.

Design and execute scalable UVM/OVM verification plans and testbenches for SoC blocks and subsystems. Develop and run emulation and system simulations, debug presilicon issues, collaborate with architects/RTL/postsilicon teams, integrate security coverage, and maintain verification infrastructure and methodologies.

Design, develop, benchmark, troubleshoot, and deploy cloud systems for Agentic AI. Integrate hardware, firmware, and software across system lifecycles, prepare technical documentation, and collaborate with cross-functional teams while staying current on LLMs, microarchitecture, and hyperscale AI deployments.

Design, develop, and optimize cloud and AI server/rack platforms by integrating software, firmware, board, and silicon components. Debug system-level issues, improve fleet quality and performance, develop automation and AI-driven engineering solutions, and collaborate cross-functionally to meet customer requirements and implement scalable, reliable systems.

Drive APJ Edge ISV adoption by identifying and onboarding ISV partners, mapping solutions to Intel Edge software, advising on architecture (OEP/Edge AI Suites), coordinating events and early-access enablement, and aligning commercial packaging and channel scale across the region.