Top Tech Jobs & Startup Jobs

Drive Intel’s XeSS and AI-based graphics technologies from research through productization. Responsibilities include designing and training models, developing datasets, evaluating visual quality, optimizing performance, and integrating products across software and hardware. The role leads technical initiatives involving super resolution, frame generation, neural rendering, and future AI graphics workloads while collaborating with research, architecture, validation, and ecosystem teams.

Designs and develops RTL for complex allocation and resource-management mechanisms in high-performance CPU cores. Owns features from microarchitecture definition through RTL implementation, validation, debugging, and tape-in readiness. Leads design efforts, evaluates architectural tradeoffs, and collaborates with architecture, verification, physical design, power-performance, and post-silicon teams. The role also involves performance analysis, power optimization, timing closure, and coverage planning.

Develop, test, debug, and maintain frontend and backend software applications. Translate user stories into scalable solutions, write functional and test code, automate build and deployment processes, perform comprehensive testing, and apply secure coding and software development lifecycle practices. Collaborate with security engineers, technical writers, product teams, and end users to define requirements, document systems, and deliver software enhancements.

Leads full-chip floorplanning, physical integration, tapeout, and physical verification for advanced-node semiconductor testchips and silicon vehicles. Develops custom layout methodologies and automation using Tcl, Python, or SKILL; resolves DRC, LVS, DFM, density, and antenna issues; collaborates with PDK, EDA, technology development, and manufacturing teams; and coordinates tape-in readiness, database integrity, and project execution for FinFET and GAA technologies.

Provides technical troubleshooting and operational support for automation applications, systems, and software running in Intel factories. Delivers next-level support across the worldwide factory network, supports application insertion hardening, and develops continuous improvement software. The role requires scripting, IT technology experience, analytical problem-solving, communication, and the ability to work independently while supporting factory operations on a compressed 12-hour day-shift schedule.

Conduct research in neuromorphic AI for edge computing, robotics, signal processing, control, and autonomous systems. Design algorithms, develop research software, build benchmarks, and optimize models for sparsity, latency, memory, quantization, and energy efficiency. Collaborate with hardware and software teams to define architectures, create customer prototypes, publish findings, and advance neuromorphic computing toward commercial applications.

Provides technical troubleshooting and operational support for automation applications, systems, and software running in Intel factories. Supports applications across the worldwide factory network, contributes to software development and insertion hardening projects, and communicates findings to factory users. The role requires independent problem-solving, multitasking across applications, and working a compressed on-site day shift schedule.

Lead a team of layout engineers developing SRAM, RF, ROM, and CAM memory compiler designs for advanced FinFET and GAA technologies. Oversee floorplanning, placement, routing, physical verification, yield, DFM, parasitic extraction, and reliability signoff. Drive layout methodology innovation and automation using SKILL, Python, Tcl, AI, and machine learning. Mentor senior engineers, manage resources, collaborate with circuit, tiling, and foundry teams, and optimize memory area, performance, power, and yield.

Design, implement, and validate high-speed analog and mixed-signal integrated circuits for silicon photonics and optical interconnect products. Responsibilities include circuit architecture, block-level design, full-chip integration, collaboration with digital and multidisciplinary teams, post-silicon test planning, and technical documentation. The role focuses on low-power, low-voltage designs supporting high-speed optical links from concept through production.

Develop and define integrated front-end and back-end process flows for new nodes; coordinate across lithography, etch, deposition, diffusion, CMP, dielectric and metrology teams; optimize RC performance; establish process windows; analyze yield loss and perform root-cause analysis using SPC/DOE/FMEA; drive corrective actions and control plans; ensure reliability margins (EM, TDDB); support R&D-to-HVM ramp and document process specifications and SOPs.