As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.
The Intel Logic Technology development (LTD) organizations deliver process technology innovation to drive Intel's product roadmap.
Job Responsibilities include but are not limited to:
• Develop and define integrated front-end and back-end process flows for new technology nodes.
• Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, dielectric, and metrology teams.
• Optimize RC (resistance-capacitance) performance.
• Establish process windows and integration schemes.
• Analyze yield loss and parametric failures.
• Perform root cause analysis using statistical tools (SPC, DOE, FMEA).
• Drive corrective actions to improve yield and cycle time.
• Implement control plans and process monitoring strategies.
• Use statistical tools such as: Cpk / Ppk, Control charts, Capability analysis
• Ensure margins for electromigration, stress migration, TDDB, time dependent via degradation.
• Evaluate impact of process window shifts on reliability.
• Support ramp from R and D to high-volume manufacturing (HVM).
• Document process specifications and standard operating procedures (SOPs).
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and or schoolwork/classes/research.
Minimum Qualifications
PhD in Electrical Engineering, Physics, Applied Physics, Materials Science, Chemical Engineering, Mechanical Engineering, Chemistry, Optics, or a closely related semiconductor field of study.
Hands-on cleanroom experience in one or more of the following:
Interconnect process development (BEOL integration)
Advanced interconnect metallization (Cu, Co, Ru, Mo, or emerging metals)
Electrical characterization of interconnect stacks (RC, EM, reliability)
Cleanroom process development in a university or industry fab environment
Preferred Qualifications
Deep understanding of RC delay, electromigration, TDDB, via resistance, and low-k dielectric integration
JMP, Python (scripting/automation), SQL, MATLAB, JSL, TCL — used for real data analysis, not just familiarity
Hands-on experience with dry etch, ALD, PECVD, CMP, metallization in a research or production fab
Demonstrated ability to design experiments, analyze results, and drive process improvements.
Strong analytical and presentation skills — ability to translate complex data into actionable engineering decisions
Familiarity with automation and defect classification systems (e.g., KLA, Applied Materials review tools).
Proven ability to influence outcomes across engineering disciplines without direct authority.
Clear, concise written and verbal communication of complex technical issues to diverse audiences.
Track record of driving projects to completion with accountability in ambiguous, fast-moving environments.
Job Type:College GradShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $103,730.00-170,630.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- PhD in Electrical Engineering, Physics, Applied Physics, Materials Science, Chemical Engineering, Mechanical Engineering, Chemistry, Optics, or closely related semiconductor field
- Hands-on cleanroom experience in interconnect process development (BEOL integration)
- Hands-on cleanroom experience in advanced interconnect metallization (Cu, Co, Ru, Mo, or emerging metals)
- Hands-on cleanroom experience in electrical characterization of interconnect stacks (RC, EM, reliability)
- Cleanroom process development experience in a university or industry fab environment
- Deep understanding of RC delay, electromigration, TDDB, via resistance, and low-k dielectric integration
- Experience using JMP, Python (scripting/automation), SQL, MATLAB, JSL, TCL for real data analysis
- Hands-on experience with dry etch, ALD, PECVD, CMP, metallization in research or production fab
- Demonstrated ability to design experiments, analyze results, and drive process improvements
- Familiarity with automation and defect classification systems (e.g., KLA, Applied Materials review tools)
- Strong analytical and presentation skills, clear written and verbal communication
- Proven ability to influence outcomes across engineering disciplines and drive projects to completion
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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