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Perform full-chip and IP physical implementation from RTL to GDSII including synthesis, place-and-route, clock tree synthesis, floorplanning, STA, power/clock distribution, signoff flows (LEC/DRC/ERC/STA), power integrity and reliability analysis, and methodology automation. Analyze results, fix violations, optimize power/frequency/area, and mentor junior engineers.

Lead and own DFT architecture and strategy for advanced FPGA/SoC/multi‑die platforms. Architect scan, ATPG, compression, MBIST/LBIST, IJTAG/JTAG, and production test flows; drive DFT methodology, cross‑functional integration, silicon debug, yield and manufacturing test optimization; mentor teams and partner with EDA vendors to deploy scalable automation and tools.

Perform end-to-end physical design implementation for custom IP and SoC from RTL to GDS, including synthesis, floorplanning, place-and-route, CTS, STA, power/noise analysis and signoff (LEC, ERC, DRC). Analyze results, fix violations, optimize power/frequency/area, and improve design methodologies and automation.

Implement physical design for custom IP/SoC from RTL to GDSII. Execute synthesis, place-and-route, CTS, floorplanning, STA, power/clock distribution, reliability and signoff (LEC/DRC/ERC). Analyze results, optimize power/frequency/area, and improve physical design methodologies and automation.

Lead global Record-to-Report functions including general ledger, month-/year-end close, reconciliations, intercompany, consolidation, fixed assets and statutory reporting. Drive process standardization, SOX compliance, ERP implementations, audits, KPI monitoring, and build a high-performing RTR team while partnering with FP&A, tax, treasury and business units.

Lead enterprise compliance for the EU Cyber Resilience Act by translating regulatory obligations into product lifecycle processes, governance, conformity evidence, and metrics. Coordinate cross-functional activities across security, engineering, quality, legal, and product teams; define SBOM and software-component traceability, vulnerability and post-market processes, conformity-assessment frameworks, training, and audit readiness. Monitor regulatory developments and support product classification, technical documentation, and executive reporting.

Manage end-to-end customer relationships for assigned accounts across lead-to-order and order-to-cash. Own order execution, escalations, demand forecasting, distributor margin, NPI/sample coordination, CRM data, and customer communications in partnership with field sales and operations.

Lead timing activities for subsystems from implementation through sign-off. Drive block and subsystem timing closure, develop STA methodologies and automation, define I/O timing budgets, run and optimize large MCMM STA, generate/validate ECOs, provide root-cause analysis and timing guidance, and collaborate with RTL, physical design, and full-chip teams.

The Product Development Engineer drives testability and manufacturability of circuits, performs yield analysis using data science techniques, and interfaces with various engineering teams to optimize silicon yield and quality.

Design, implement, and validate FPGA configuration architecture and subsystems. Develop configuration RTL/firmware and interfaces, support JTAG/SPI/CvP schemes, debug bitstream and bring-up issues, collaborate across architecture, software, and validation teams, and maintain specifications and test documentation.