The Role
Implement physical design for custom IP/SoC from RTL to GDSII. Execute synthesis, place-and-route, CTS, floorplanning, STA, power/clock distribution, reliability and signoff (LEC/DRC/ERC). Analyze results, optimize power/frequency/area, and improve physical design methodologies and automation.
Summary Generated by Built In
Job Details:Job Description:
- Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
- Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
- Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
- Analyzes results and makes recommendations to fix violations for current and future product architecture.
- Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
- Optimizes design to improve product-level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Education Requirements:
Bachelor's degree in computer engineering, electronic Engineering or related field.
Bachelor's degree in computer engineering, electronic Engineering or related field.
Minimum Qualifications
3+ years of relevant experience in the following areas:
- Have multiple tape-out experience in deep submicron process nodes
- in depth, extensive knowledge and hands-on experience in physical design flow and relevant EDA tools
- in depth, extensive knowledge and hands-on experience in physical design signoff flow, such as STA flow, LEC flow, ERC flow and DRC flow.
- Hands-on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages of VHDL and Verilog.
- Experience of mentoring junior team members and charting their development for success.
- Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Preferred Requirements:
- Bachelor or master's degree in computer engineering, Electronic Engineering or related field.
- 3+ years of experience in the following areas:
- Physical design involving multiple clock domains and clock, power management.
- Low power design, tools and methodologies. Power intent UPF specifications.
Skills Required
- Bachelor's degree in computer engineering, electronic engineering or related field.
- 3+ years of relevant experience in physical design and tape-outs.
- Multiple tape-out experience in deep submicron process nodes.
- In-depth, hands-on experience in physical design flow and relevant EDA tools (synthesis, place and route, CTS, floorplanning).
- In-depth, hands-on experience in physical design signoff flows (STA, LEC, ERC, DRC).
- Hands-on expertise with scripting languages such as Perl, TCL, Python.
- Knowledge of hardware description languages VHDL and Verilog.
- Experience mentoring junior team members.
- Strong initiative, analytical/problem-solving skills, teamwork, and ability to multitask.
- Experience with physical design involving multiple clock domains and power management.
- Low power design tools and methodologies; power intent (UPF) specifications.
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
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The Company
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
