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Perform block-level physical implementation of custom IP and SoC designs from RTL to GDSII. Execute synthesis, floorplanning, P&R, CTS, STA, and physical verification. Resolve timing, power, and signal-integrity issues, support DFT integration and signoff, and develop/automate physical design methodologies to optimize PPA and manufacturability.

The Internal Sales Representative supports field sales by managing customer relationships, processing orders, coordinating with cross-functional teams, and preparing sales reports.

Lead physical implementation and STA for advanced FPGA SoCs from floorplanning through final timing closure. Drive block- and SoC-level implementation, develop SDC/UPF constraints, perform MMMC STA with PrimeTime, resolve timing/physical violations, execute signoff/physical verification, build Tcl/Python automation and evaluate ML/AI-assisted flows, and mentor engineers while coordinating with RTL, CAD, library, and packaging teams.

Develop and execute DFT and test-logic verification plans for FPGA SoC/IP. Build and maintain SystemVerilog/UVM testbenches, run functional/regression and coverage-driven verification, debug RTL/testbench failures, collaborate with architects and design teams, and track verification metrics.

Develop and execute verification plans and reusable SystemVerilog/UVM testbenches for FPGA IP, subsystems, and SoC designs. Create constrained-random and directed tests, SVA assertions, and coverage models; debug failures via simulation/emulation; collaborate with RTL, firmware, and validation teams to achieve verification closure and support post-silicon bring-up.

Lead architecture, microarchitecture, RTL design, and technical direction for scalable Network-on-Chip IPs for FPGA platforms. Develop RTL, prototypes, simulation models, and software bring-up; optimize for power, performance, area, and reliability. Guide verification, collaborate with cross-functional teams, mentor engineers, and apply EDA and AI-enabled automation to meet project schedules and quality goals.

Lead thermal and thermomechanical characterization and qualification of advanced 2.5D/3D semiconductor packages. Develop and calibrate FEA models, define and run warpage/coplanarity/reliability tests, perform lifetime prediction and failure analysis, own DFMEA activities, and produce customer reports on package reliability.

Lead end-to-end SI/PI design and verification for high-speed interconnects across silicon, package, and board. Define simulation methodologies, run DOE, establish SI/PI design rules, review layouts, perform post-layout simulations, and collaborate with silicon, package, and board teams to optimize SERDES, memory interfaces, FPGA fabric, and PDNs using advanced EDA tools and AI-assisted techniques.

Responsible for timing closure and signoff of FPGA/SoC and subsystem timing via static timing analysis. Derive and provide interface timing constraints, perform final timing signoff, and collaborate with design, architecture, and physical design teams for timing convergence and closure.

12-month interim Internal Sales Representative supporting field sales and FAEs. Manage Lead-to-Order and Order-to-Cash processes, customer account management, order management, pricing/quote requests, escalations, distributor coordination, demand collection and sales forecasting, CRM data maintenance, NPI/sample coordination, sales reporting, and onboarding support.