SOC Timing Engineer

Reposted 3 Days Ago
Be an Early Applicant
Penang, Daerah Timor Laut, Penang, MYS
In-Office
Mid level
Artificial Intelligence • Internet of Things • Machine Learning
The Role
Responsible for timing closure and signoff of FPGA/SoC and subsystem timing via static timing analysis. Derive and provide interface timing constraints, perform final timing signoff, and collaborate with design, architecture, and physical design teams for timing convergence and closure.
Summary Generated by Built In
Job Details:

Job Description:
  • As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
  • Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
  • Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure 

Qualifications:

 Experience in Static timing analysis , and industry standard EDA tools like Primetime/PTPX  

- Good understanding of timing constraints, clocking, PVT etc 

- Should have tapeout experience including in latest technology 10nm or lower 

- BE/MS/Phd in Electronics/Electrical Engineering with 3+ Years' experience in physical design and timing closure/signoff  

-Candidate should be strong in communication, problem solving and analytical skill 

Job Type: Regular

Shift:Shift 1 (Malaysia)

Primary Location:Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Skills Required

  • Experience in Static Timing Analysis
  • Experience with industry-standard EDA tools such as PrimeTime and PTPX
  • Good understanding of timing constraints, clocking, PVT
  • Tapeout experience including advanced nodes (10nm or lower)
  • BE/MS/PhD in Electronics/Electrical Engineering
  • 3+ years experience in physical design and timing closure/signoff
  • Strong communication, problem solving and analytical skills

Altera (altera.com) Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).

  • Retirement Support Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
  • Leave & Time Off Breadth Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
  • Parental & Family Support Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.

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The Company
HQ: San Jose, California
1,612 Employees
Year Founded: 1983

What We Do

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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