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The Senior IC Layout Mask Designer will lead the layout design for high-performance analog cores in cutting-edge CMOS processes. Responsibilities include floor planning, routing, and assembly of silicon chips, utilizing industry-standard EDA tools, and implementing advanced layout techniques for optimum performance.

As a Senior IC Layout Mask Designer, you will lead layout activity for high performance analog cores and establish layout procedures. Responsibilities include working with industry-standard EDA tools, layout for high performance analog blocks, and managing layout team activities.

The Senior DFT Engineer will drive DFT flows for digital designs, collaborating with RTL and physical design teams to enhance testability. Responsibilities include defining DFT strategies, creating test structures and vectors, and resolving design issues related to DFT. The role requires hands-on experience with test generation tools and a strong understanding of digital ASIC design.