Role and Responsibility
- Lead the SOC and Mixed signal verification team and efforts
- Build capable verification team and manage the tasks and the team to get to tape out on agreed upon schedule and to Production with Agreed upon turns. Revision 0 Silicon success is highly desired.
- Develop and signoff on test plans and test cases
- Strong knowledge of digital design and two or three of AMBA AHB/AXI/APB based SoC Architecture, ADC/DAC, PCIe, Ethernet, CAN, LPDDR interfaces.
- strong knowledge of Verilog, System Verilog, UVM, C/C++
- Experience in usage of assertions, constrained random generation, functional/code coverage
- Knowledge of scripting languages like Perl, Python, TCL, Linux shells to achieve automation of verification methodologies and flows
- Analytical debugging skills
- Excellent team building and management skills
Qualifications and Experience
- BS in EE with 8+ years of experience or MS in EE with 6+ year experience
- Knowledge of at least one of high-speed interfaces like USB, MIPI, PCIe, Ethernet, DP,
- Knowledge of two or three of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, SPI
- Experience managing a verification team
- Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
- Fluent in verification languages such as UVM/OVM/System Verilog, Vera, Verilog
- Experience in writing Test-plans and creating directed and random test cases
- Strong scripting skills in Perl, Python, Linux shells etc.
- Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure
- Strong analytical problem solving and attention to details
- Team player with interest in filing up gaps in product development as needed
- Good written and verbal communication skills
- Good technical documentation skills
- Good interpersonal skills, self-motivated, self-starter
Expectations
- Develop the Test benchses for AMS and FC simulations
- Be UPF Aware.
- Develop the tests to get 95+% coverage for the simulations
- Work with Design team to debug any failures
- Integrate and run the BIST and DFT gate level sims.
- Do code, line and toggle coverage and other metrics.
- Run daily and weekly regressions and publish results
- Responsible for FC RTL, Gate level simulations
- Be a mentor and lead a team of Verification engineers
- Work with Systems and Test engineering team to help validate the parts and release them to production
Top Skills
What We Do
Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores in advanced FinFET nodes to 28nm, that enable differentiated systems-on-chip (SoCs) in applications ranging from 5G, wireline and optical communications, LiDAR, radar, networking, AI, image sensors, and IoT. Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few Msps to over 20 Gsps sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins, Colorado, Boston, Massachusetts and Bangalore, India.
