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23 Days Ago
DKI Jakarta, Gambir, DKI Jakarta, IDN
638 Employees
Entry level
638 Employees
Entry level
HR Tech • Information Technology
The Risk Manager will analyze data to develop risk management strategies, build monitoring dashboards, collaborate with teams on risk management, investigate risk events, and optimize risk frameworks.
23 Days Ago
Fremont, CA, USA
638 Employees
110K-300K Annually
Senior level
638 Employees
110K-300K Annually
Senior level
HR Tech • Information Technology
The ASIC/SoC Design Verification Engineer will define and implement test plans for SoC design verification, develop reusable test benches and verification modules, and mentor junior engineers while collaborating with design teams. Key responsibilities include building verification infrastructure and debugging simulation failures, ensuring efficient and effective verification processes.
23 Days Ago
Fremont, CA, USA
638 Employees
110K-300K Annually
Expert/Leader
638 Employees
110K-300K Annually
Expert/Leader
HR Tech • Information Technology
The Analog/Mixed-Signal IC Design Engineer is responsible for designing and developing high-performance analog integrated circuits, conducting simulations and validations, collaborating with teams for integration, and mentoring junior engineers. They support testing and debugging of ICs and ensure proper documentation of designs and methodologies.
23 Days Ago
Fremont, CA, USA
638 Employees
110K-300K Annually
Senior level
638 Employees
110K-300K Annually
Senior level
HR Tech • Information Technology
The Memory Circuit Design Engineer will design memory IC projects, define and implement memory architectures, create test plans, troubleshoot design issues, collaborate with engineering teams, investigate design-related issues, and ensure quality validation processes. They will stay updated on industry advancements and maintain documentation throughout projects.
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