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Lead architecture and design of ML-centric SoCs and accelerators, defining compute fabrics, memory hierarchies, ISA/compiler co-design, prototyping on FPGA/ASIC, security architectures, and guiding cross-functional teams to validate and scale domain-specific ML solutions.

The role involves designing and developing analog and mixed-signal IC blocks, supporting product validation, and collaborating with cross-functional teams.

The Staff Package Design Engineer will create packaging solutions for high-performance products, collaborate with teams, and drive design improvements and validation processes.

The Staff Package Design Engineer will develop packaging solutions, collaborate with cross-functional teams, and ensure design rules are met while improving processes and efficiency in the design flow.

Lead mixed-signal verification for complex ICs: define verification strategy, develop reusable testbenches and behavioural models (SystemVerilog, VerilogA/AMS), perform hands-on simulation/netlisting, support tools/methodology, mentor engineers, and collaborate across disciplines to ensure first-time-successful deliveries.

Lead product definition and system architecture for industrial ICs, conduct feasibility and teardown analyses, translate customer needs into system requirements, influence technical direction, support customer engagements and represent the company at industry forums.

Develop and implement digital subsystems for mixed-signal ICs, supporting integration and verification while collaborating with cross-functional teams to ensure manufacturable designs.

As a Digital Design Engineer, you will design and implement digital subsystems for mixed-signal ICs, develop RTL designs, and perform verification and post-silicon validation.

Lead and build a Taipei-based embedded system test team to define and execute post-silicon system test strategies (functional, stress, endurance, negative, system-level), drive test automation and CI, partner with firmware/driver/systems/product teams for validation and defect triage, and represent system test quality to internal and external stakeholders including ODMs and customers.

Responsible for end-to-end functional verification of mixed-signal ASICs, developing verification plans, testbenches, coverage analysis, and collaborating with cross-functional teams.