Principal SoC Architect (ML Accelerators)

Responsibilities

• Architecture Leadership: Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, memory hierarchies, and integration with mixed-signal front ends.
• Cross-Domain ML Enablement: Translate domain-specific requirements (voice interaction, sensor analytics, motor control) into architectural specifications and accelerator designs.
• Exploration & Tradeoff Analysis: Lead architectural exploration of performance, power, area, and cost tradeoffs; create models and benchmarks for workload-driven analysis.
• ISA & Compiler Co-Design: Collaborate closely at the instruction set and compiler/toolchain level to ensure that the ISA, micro-architecture, and runtime stack are co-optimized for ML workloads and domain-specific kernels.
• Prototype & Validation: Partner with internal engineering, startups, and research institutions to rapidly prototype candidate architectures on FPGA/ASIC platforms and validate with representative workloads.
• Security Architecture: Define and evaluate on-chip security architectures, including trusted execution environments (TEE), enclaves, memory partitioning, and hardware root-of-trust, ensuring robust protection for ML-enabled SoCs.
• Technology Scouting: Evaluate external IP, startups, and research in ML accelerators; identify opportunities for partnership, licensing, or incubation.
• Advisory & Influence: Serve as a technical advisor across multiple CVL initiatives; mentor engineers, guide innovation managers, and influence long-term compute strategy.
• Customer & Market Alignment: Work backwards from customer problems to ensure architectures are not only performant, but also scalable, integrable, and monetizable in real-world systems.
• Thought Leadership: Publish architectural principles, drive internal alignment around ML-enabled mixed-signal processing, and represent CVL in industry and academic forums.

Required Skills and Qualifications

• Educational Background: Ph.D or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field.
• Experience: 10+ years in SoC or accelerator design, with a focus on ML, DSP, or high-performance edge compute.
• Technical Expertise: Deep understanding of ML accelerator architectures, including systolic arrays, SIMD/VLIW, RISC-V/ARM integration, memory subsystems, and dataflow optimization.
• ISA & Compiler Co-Design: Hands-on experience defining ISAs or ISA extensions and collaborating with compiler/runtime teams to tightly couple software to hardware micro-architecture.
• Mixed-Signal Awareness: Familiarity with the architectural implications of coupling ML compute with analog/mixed-signal front ends.
• System Modeling: Strong experience in architectural modeling, workload benchmarking, and system-level tradeoff analysis.
• Prototyping Tools: Expertise with simulation, emulation, FPGA prototyping, and performance modeling frameworks.
• Collaboration: Proven track record of working with cross-functional teams spanning hardware, software, research, and business.
• Communication Skills: Ability to clearly articulate complex architectural concepts to both technical and non-technical audiences, including executives.

Preferred Skills and Qualifications

• Security Architecture Expertise: Experience in hardware-level security stacks, including TEEs, enclaves, memory isolation schemes, secure boot, and cryptographic accelerators.
• Startup/Incubator Experience: Experience driving early-stage architectural concepts from exploration through to prototype.
• Low-Power Design: Expertise in energy-efficient architectures for edge workloads.
• External Engagement: Strong network in academia and industry in ML accelerators, SoC design, or edge AI.
• Patents & Publications: Demonstrated thought leadership through IP generation and publications in top-tier conferences/journals.
• Agile & Lean Innovation: Familiarity with agile practices for rapid prototyping and early product validation.