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Design and implement digital subsystems for mixed-signal integrated circuits, collaborate with cross-functional teams, and lead verification processes.

The role involves functional verification of ASIC designs, including developing verification plans, testbenches, and collaborating with cross-functional teams to ensure high-quality outcomes.

Design and implement digital subsystems for mixed-signal ICs, developing RTL designs and ensuring proper integration with analog circuitry, while supporting verification and post-silicon validation.

Lead and execute digital verification for mixed-signal ICs: define verification plans, create reusable testbenches, drive metric-driven verification, mentor teams, and improve verification methodology.

Lead transistor-level mixed-signal CMOS IC design from concept through production, including modeling, layout oversight, post-layout simulation, lab silicon debug, and supporting product validation and production test.

Lead architecture and design of ML-centric SoCs and accelerators, defining compute fabrics, memory hierarchies, ISA/compiler co-design, prototyping on FPGA/ASIC, security architectures, and guiding cross-functional teams to validate and scale domain-specific ML solutions.

Conduct research and prototype signal-processing software and algorithms, collect and analyze lab data, write MATLAB simulations and C implementations, define functional requirements, estimate resource footprints, run controlled experiments, prepare technical reports, and support patenting of developed technologies.

Design and model advanced power conversion circuits from specification to silicon, implement transistor-level designs, oversee layout and post-layout simulation, perform hands-on silicon lab debugging, and support post-silicon validation, characterization, and production testing.

Lead integration and deployment of Cirrus audio drivers and tooling on customer Windows/Linux platforms. Define integration strategies, triage and debug customer issues, support platform bring-up, mentor engineers, and coordinate cross-functional teams to deliver feature updates and customer enablement.

Design, insert, and verify DFT features including memory BIST and scan. Generate ATPG patterns, perform gate-level verification, improve test coverage, plan test costs, and deliver patterns to product test and ATE for silicon bring-up.