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Astera Labs is seeking a Senior Design Verification Engineer with expertise in System Verilog, C, C++, and Python. The role involves full lifecycle verification of complex ASICs, test planning, debugging, and coverage collection. Strong academic background in electrical engineering and a minimum of 5 years' experience in verifying SoCs for Server, Storage, and Networking applications are required. The position offers a base salary range of $130,000 - $185,000 per year.