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The Principal Product Applications Engineer will engage with customers, support PCIe product adoption, troubleshoot system issues, and create technical documentation while collaborating with cross-functional teams.

The Principal Physical Design Engineer will oversee end-to-end STA ownership, coordinating and executing design processes for connectivity ASICs while ensuring robust timing closure and collaboration with various engineering teams.

Drive customer success for Taurus Ethernet solutions through technical engagement, debugging complex issues, and collaborating with internal teams for product evolution.

Astera Labs seeks talented professionals in various disciplines for future openings, focusing on hardware, firmware, software, program management, and operations.

Develop, optimize, and maintain embedded firmware for optical engines and photonic integrated circuits, including control and calibration of optical modules and high-speed link optimization.

The Principal Digital Design Engineer will architect and implement advanced digital designs for AI connectivity, manage complex design blocks, and drive RTL implementations, ensuring production-quality silicon for high-speed protocols.

Lead customer-facing technical engagements for optical connectivity, driving solution adoption, link bring-up, debug, and system validation. Partner with silicon, firmware, hardware, and optical module partners to develop test methodologies, documentation, and field enablement while mentoring engineers and representing the company at industry forums.

The Senior Principal Engineering Program Manager will lead ASIC product development, ensuring timely execution, risk management, and cross-functional alignment across various teams to deliver revenue-critical silicon solutions.

The Senior Principal Technologist will drive the architecture and development of data center memory solutions, engage with customers, and influence product features using expertise in system and memory architecture and technologies.

Lead DFT strategy and execution for multi-die PCIe switch products using 2.5D/3D packaging. Define test architecture, implement scan/ATPG/MBIST/LBIST, drive fault coverage targets, optimize production test and ATE costs, collaborate across design, packaging, validation, and manufacturing to ensure yield, reliability, and production ramp.