Top Tech Jobs & Startup Jobs

Lead IR drop and electromigration (EMIR) analysis and sign-off for advanced-node SoCs from floorplan through tapeout. Collaborate with power grid, floorplan, package, implementation, RTL, STA, IP vendors and foundry to resolve hotspots, guide mitigation (decap, grid reinforcement), and deliver automated EMIR flows, runsets, and root-cause reporting for multi-corner sign-off.

Design and optimize power delivery systems for ASICs, ensuring power integrity and collaborating with vendors. Responsibilities include circuit design, debugging, and documentation.

Lead the development and implementation of optical and electro-optical testing for Co-Packaged Optics solutions, ensuring performance and reliability while mentoring junior engineers.

Lead end-to-end corporate development transactions (acquisitions, investments, partnerships), perform valuation and strategic analysis, manage diligence and integration across functions, produce board-ready materials, and monitor AI infrastructure market trends to inform executive strategy.

Serve as the primary technical interface for strategic customers, supporting custom silicon programs from architecture through production. Lead system-level debug across hardware, firmware, and software; translate customer requirements into engineering actions; develop diagnostics, reference designs, and documentation; collaborate with cross-functional teams and travel to customer sites to drive deployments and design wins.

Act as the technical bridge between customers and engineering to support custom silicon programs from architecture through production. Lead system-level debug, silicon bring-up, validation, and deployment. Translate customer requirements into engineering actions, produce technical collateral and tools, and collaborate across product, ASIC, firmware, validation, and software teams to drive customer success and influence future silicon.

The Senior Director will lead product technical ownership, driving chip development, cross-functional leadership, and processes within a growing AI technology company.

Lead RTL design and implementation for complex connectivity IP blocks from microarchitecture to synthesis sign-off. Partner with architecture, verification, DFT, and physical design to achieve timing closure and silicon readiness. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, PPA-focused deliverables for PCIe/CXL/Ethernet-based SoC integration.

Lead strategic customer engagements and commercial negotiations with hyperscalers and AI platform providers to convert opportunities into long-term agreements. Drive cross-functional alignment, create regional/segment playbooks, develop market insights, and implement scalable processes to accelerate revenue growth and strategic partnerships in the semiconductor connectivity and AI infrastructure space.

Lead the go-to-market strategy for PCIe signal conditioning products, driving market positioning, execution, and revenue growth while collaborating with cross-functional teams and mentoring staff.