Top Tech Jobs & Startup Jobs

Own end-to-end RTL-to-GDS physical design for advanced-node, high-performance SoCs, including synthesis, floorplanning, placement, clock-tree synthesis, routing, timing, power, physical verification, and tapeout signoff. Lead methodology development, ECO closure, and cross-functional integration with RTL, DFT, analog, package, and CAD teams. Mentor engineers and guide technical decisions across complex connectivity silicon programs.

Designs and implements front-end digital circuits for high-performance networking and switch ASICs, including microarchitecture, RTL, synthesis, IP integration, verification, timing closure, DFT, and silicon bring-up. Owns complex designs from architecture through GDS and production while working with PCIe, UALink, Esun, and Ethernet protocols. Requires expertise with Synopsys or Cadence flows, UVM verification, small-geometry CMOS, and customer-focused technical leadership.

Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, data conversion, references, and regulators. Lead designs from architecture through verification, silicon bring-up, characterization, and debug in advanced FinFET processes. Establish design methodologies, collaborate across engineering teams, conduct technical reviews, and mentor analog engineers developing connectivity products for AI infrastructure.

Architects and maintains ASIC and SoC emulation environments for pre-silicon validation. Integrates RTL, transactors, protocol models, software, and test infrastructure for hardware-software co-simulation. Verifies PCIe, Ethernet, memory, storage, and other interfaces; develops reusable models, tests, checkers, and debug methods; analyzes coverage and performance; and leads cross-functional debugging across design, verification, firmware, and systems teams.

Own physical design and signoff for complex connectivity ASICs from RTL through GDS. Drive synthesis, place-and-route, extraction, timing closure, ECOs, EM-IR, Formality, and DRC/LVS across blocks and full chips. Collaborate with RTL, verification, implementation, and top-level teams on constraints, clocking, I/O timing budgets, hierarchical models, and convergence. The role requires advanced-node experience, high-speed SERDES/DDR knowledge, scripting, and proficiency with Cadence or Synopsys toolchains.

Partner with R&D business unit leadership to manage annual budgets, quarterly forecasts, and performance analysis. Develop financial models, interpret results versus budget, assess risks, and provide strategic recommendations. Collaborate with Corporate Finance and support business analysis and process improvements.

The Product Quality Engineer will perform failure analysis, drive root-cause identification, collaborate with teams, and utilize lab instrumentation to ensure high-quality AI connectivity solutions.

Lead global pricing and monetization strategy for semiconductor, software, and connectivity products. Build pricing governance, policies, approval workflows, and pricing models. Partner cross-functionally with Product, Finance, Sales, and Executive Leadership, engage in senior customer negotiations, develop pricing metrics and reporting, and scale a pricing function to support profitable growth and competitive positioning.

Lead formal verification strategy and methodology for next-generation connectivity products. Develop formal models, assertions, and test plans; apply EDA tools and complexity-reduction techniques to find corner-case bugs. Mentor global engineers, collaborate with design teams, and represent the company in industry forums.

The Principal Digital Design Engineer will architect and implement complex digital designs for connectivity solutions, oversee micro-architecture and RTL implementation, and mentor junior engineers.