Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
As an Astera Labs STA Physical Design Engineer, Senior Principal you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.
Key Responsibilities
- Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems.
- Identify RTL issues early and work with frontend team on resolution.
- Hands-on experience with various custom clocking techniques.
- Experience with high-speed designs with serdes/ddr IPs.
- Good understanding of PnR tool and signoff flows like Extraction, STA, Formality, EM-IR and DRC/LVS etc
- Hands-on experience with ECO flow using PT DMSA and hyperscale models for bigger chips
- A good understanding of SDC constraints, be able to interact with design team on constraints refinement.
- Work with top level owners on defining and managing I/O timing budgets across hierarchical designs.
- Knowledge of different ways to build hierarchical design (black-box model, ETM or abstract model etc).
- Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.
Basic Qualifications
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
- ≥10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
- Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
- Strong scripting ability (Tcl, Python, Perl).
- Ability to work independently with strong prioritization and a professional, customer-focused mindset.
Preferred Experience
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
- Experience working with IP vendors for both RTL and hard-macro integration.
- SystemVerilog/Verilog familiarity.
The base salary range is USD 207,000.00 USD – USD 230,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering or Computer Science
- At least 10 years of experience in place-and-route and signoff for complex SoCs
- Experience with server, storage, or networking applications
- Expertise in place-and-route, extraction, timing closure, EM-IR, Formality, and DRC/LVS at block and full-chip levels
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence-checking flows in 7nm or smaller advanced nodes
- Proficiency with Cadence and/or Synopsys physical design and STA toolchains
- Strong scripting ability in Tcl, Python, or Perl
- Ability to work independently with strong prioritization and a professional, customer-focused mindset
- Master's degree
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis
- Experience working with IP vendors for RTL and hard-macro integration
- Familiarity with SystemVerilog or Verilog
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
