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Leads and develops a US-based technical program management team responsible for advanced ASIC programs from architecture through production release. Oversees milestone planning, dependencies, execution reviews, risk mitigation, budgeting, resource allocation, and readiness for tapeout, power-on, validation, qualification, and manufacturing. Partners with engineering, executives, customers, and external partners while driving consistent reporting, accountability, and cross-functional issue resolution.

Develop microarchitecture and front-end digital designs for high-performance networking and switch ASICs. Own RTL, synthesis, IP integration, verification, timing closure, DFT, and block or full-chip implementation through GDS and production. Apply PCIe, UALink, Esun, and Ethernet protocol expertise while using Synopsys or Cadence flows. Support silicon bring-up and debugging, collaborate with customers, and drive multiple complex designs with minimal supervision.

Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, and high-speed I/O products. Lead designs from specification through schematic, layout supervision, verification, silicon bring-up, characterization, and debug. Establish design methodologies, collaborate across engineering teams, and mentor analog engineers. The role requires advanced CMOS/FinFET design expertise, physical-layer and signal-integrity knowledge, and proficiency with industry-standard simulation tools.

Own strategic partnerships with CPU platform providers, ODMs, OEMs, and system integrators. Drive roadmap alignment, interoperability, reference designs, joint business planning, partner agreements, co-marketing, sales enablement, and ecosystem-influenced design wins. Translate AI infrastructure technologies into compelling rack-scale solutions, influence product and go-to-market strategy, present to executives and customers, and represent the company at industry events. The role is based onsite in San Jose five days weekly and requires approximately 25% travel.

Leads customer and internal deployment of high-performance PCIe fabric solutions for AI infrastructure. Responsibilities include defining architectures, developing reference designs, driving system bring-up and interoperability debugging, partnering on firmware configuration and recovery, analyzing protocol and performance issues, building validation automation, and leading cross-functional root-cause resolution from prototype through production.

Leads hardware NPI programs from design release through validation, manufacturing readiness, customer preparation, and launch. Owns integrated schedules, budgets, dependencies, risks, readiness reviews, and cross-functional execution across engineering, manufacturing, supply chain, quality, finance, operations, customers, and suppliers. Drives PCB/PCBA builds, supplier and contract manufacturer coordination, issue resolution, dashboards, process improvements, workflow automation, and executive communication. Coaches teams and supports predictable delivery of AI infrastructure connectivity hardware.

Develop front-end digital designs for high-performance network controllers, including microarchitecture, RTL, synthesis, IP integration, verification, timing closure, DFT, and silicon bring-up. Own complex SoC and ASIC designs from architecture through GDS and production while supporting high-speed protocols such as PCIe, UALink, and Ethernet. Collaborate with customers and internal teams, debug silicon, and use Synopsys or Cadence design flows.

Lead end-to-end test engineering for mixed-signal silicon and high-speed connectivity products, from product definition through high-volume manufacturing. Define test strategies, architect and validate tester hardware, optimize coverage, yield, cost, and test time, and resolve complex failures using lab and manufacturing data. Partner across design, DFT, product engineering, operations, quality, and manufacturing while mentoring engineers and guiding technical decisions.

Develop proactive executive talent strategies for Astera Labs by partnering with senior leaders, analyzing semiconductor and silicon talent markets, building executive pipelines, and leading searches from strategy through close. The role advises VP, C-suite, and board-level stakeholders on organizational needs, leadership profiles, assessment criteria, succession planning, and future hiring priorities. This is a fully in-person position in San Jose.

Lead RTL design and implementation for complex connectivity IP blocks from microarchitecture to synthesis sign-off. Partner with architecture, verification, DFT, and physical design to achieve timing closure and silicon readiness. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, PPA-focused deliverables for PCIe/CXL/Ethernet-based SoC integration.