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The FP&A Business Unit Controller manages R&D units' financial processes, annual budgets, forecasts, and provides analytical insights to senior leadership.

Responsible for the full lifecycle of verification of complex ASICs, including planning, writing tests, debugging, coverage collection, and working with teams to execute test plans on emulation platforms.

Lead the go-to-market strategy for PCIe signal conditioning products, driving market positioning, execution, and revenue growth while collaborating with cross-functional teams and mentoring staff.

Seeking a Senior Principal Product Manager to lead product roadmap for Astera's connectivity solutions, involving software, firmware, and silicon integration. The role includes engaging with customers, defining strategies, and overseeing cross-functional execution to improve manageability in AI infrastructure.

Lead capacity planning and scenario modeling across product lines and manufacturing partners. Build and maintain ETL pipelines, API integrations, Oracle reports, and Power BI dashboards to surface shortages, capacity risks, and recovery plans. Produce 18-month rolling forecasts, run constraint-based production plans, and drive cross-functional initiatives to resolve bottlenecks. Support NPI ramps and communicate risks and recommendations to stakeholders and leadership.

Lead architecture and development of firmware and microcontroller subsystems for SoC and system products. Implement differentiating features, collaborate with logic designers to define and verify HW–SW interfaces, develop on-chip MCU firmware and C-based SDKs for system controllers (BMC), debug PCIe protocol issues, automate workflows with Python, and maintain build/documentation toolchains. Customer-facing and requires strong prioritization.

Lead strategic customer engagements and commercial negotiations with hyperscalers and AI platform providers to convert opportunities into long-term agreements. Drive cross-functional alignment, create regional/segment playbooks, develop market insights, and implement scalable processes to accelerate revenue growth and strategic partnerships in the semiconductor connectivity and AI infrastructure space.

As a Principal Digital Design Engineer, you'll lead the development of high-speed SerDes transceivers for AI systems, managing design specifications and RTL delivery, collaborating with various teams, and optimizing for performance and power.

The Staff Design Verification Engineer is responsible for the full verification lifecycle, developing tests and collaborating with RTL designers to ensure high-quality ASIC designs for AI connectivity.

The Senior Principal Digital Design Engineer leads digital design architecture for AI connectivity, guiding teams through design execution and cross-functional collaboration while mentoring engineers to ensure high-quality production deliveries.