Principal Product Technical Leader — AEC/SCM

Reposted Yesterday
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San Jose, CA, USA
In-Office
133K-185K Annually
Senior level
Big Data • Information Technology
The Role
Lead RTL design and implementation for complex connectivity IP blocks from microarchitecture to synthesis sign-off. Partner with architecture, verification, DFT, and physical design to achieve timing closure and silicon readiness. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, PPA-focused deliverables for PCIe/CXL/Ethernet-based SoC integration.
Summary Generated by Built In

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a hands-on Principal Product Technical Leader to drive product integration for Active Electrical Cables (AECs) and Smart Cable Modules (SCMs) used in rack-scale AI infrastructure. You will serve as a technical owner across high-speed silicon and retimers, firmware, PCB or flex circuitry, cable assemblies, connectors, mechanical and thermal design, signal integrity, validation, manufacturing, and customers.

You will translate system and customer requirements, engineering data, and field feedback into reliable, production-ready products. This is an individual-contributor role: you will lead complex technical investigations, resolve cross-domain issues, strengthen product readiness, and improve repeatable integration and debug practices. You should bring deep expertise in at least one relevant discipline and working knowledge across adjacent domains.

Key ResponsibilitiesProduct integration and validation
  • Define product-level interfaces, integration plans, risks, validation checkpoints, and readiness criteria from design through production release.
  • Influence architecture and design decisions early, finding creative, practical solutions to tradeoffs across signal integrity, retimer and firmware integration, power, thermal performance, mechanical constraints, manufacturability, cost, and schedule.
  • Lead product-level electrical compliance and system validation for AEC/SCM products, including channel performance, eye margins, jitter, equalization, link training, BER, interoperability, and resolution of system-level issues.
  • Direct and review AEC/SCM hardware validation, including board-level probing, circuit verification, functional testing under nominal, corner, mechanical, and environmental conditions, and reliability/failure analysis; ensure results are correlated to design requirements and corrective actions are driven to closure.
  • Drive root-cause analysis for issues spanning silicon, firmware, hardware, SI, mechanical, thermal, test, and manufacturing teams.
Production readiness and technical execution
  • Partner with NPI, manufacturing, quality, and operations teams to transition products from development into volume production.
  • Drive DFM/DFA/DFT reviews, production-test development, test-coverage improvements, yield analysis, and manufacturability feedback.
  • Own technical investigations and corrective actions for complex failures, process excursions, production escapes, and field issues.
  • Establish clear product specifications, issue-tracking practices, technical reports, and readiness reviews.
Customer and cross-functional leadership
  • Provide technical direction during customer bring-up, interoperability testing, platform qualification, and escalations.
  • Collaborate with applications and customer engineering teams to resolve design-in challenges and translate field feedback into product improvements.
  • Lead cross-functional design and integration reviews across hardware, firmware, SI, mechanical, test, manufacturing, and quality.
  • Mentor engineers and improve documentation, debug workflows, integration methods, and engineering standards.

The base salary range is $160,000 USD - $200,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.


We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Skills Required

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • 5+ years of digital design experience, including at least one full chip from spec to tapeout
  • Proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
  • Hands-on experience with timing closure, CDC, lint, and low-power design techniques
  • Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
  • MS or PhD in Electrical Engineering or Computer Engineering
  • Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
  • Familiarity with formal verification, emulation, or assertion-based methodologies
  • Background in advanced process nodes (7nm, 5nm, or below) and strong pre-/post-silicon debug skills

Astera Labs Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.

  • Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
  • Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
  • Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.

Astera Labs Insights

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The Company
HQ: San Jose, CA
148 Employees
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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