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Perform full-chip and block-level physical design and verification for low-power AI SoCs from netlist to GDSII, including floorplanning, place-and-route, STA, ECO implementation, signal integrity and EM/IR analysis, and LVS/DRC/DFM physical verification.

Design and implement video compression, image processing, vector compute, processor cores, and memory subsystems in SystemVerilog/Verilog. Optimize RTL for timing, area, and power, develop front-end methodologies, model micro-architecture with scripting, support verification/coverage analysis, and participate in chip bring-up and testing.