Job Description
The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII.
The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.
Requirements
- BS/MS in EE/computer science or equivalent experience
- 3- 5+ years’ experience,
- Good understanding in VLSI digital design/Layout/Timing closure
- Basic knowledge on circuit design, device delays, and timing at gate-level
- Familiar with industry EDA tools such as Cadence Innovus/Quantus/Tempus, Synopsys Fusion Compiler/ICC2/StarRC/Primetime and Mentor Calibre.
- Proficient programming and scripting skills (Perl, Python, TCL, C-shell, make)
- Hardware Design Languages like Verilog, VHDL
- Self-motivated team worker, good verbal and written interpersonal skills.
- Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC would be an added advantage.
- Solid understanding of hierarchical physical design strategies, methodologies and nanometer advanced node technology issues.
- Hands-on experience in STA including multi-mode multi-corner analysis and ability to analyze and fix critical timing issues.
- Proven track record of delivering tape-out quality GDSII with silicon success in sub 10 nm is a plus.
The base salary range is $140,000 - $156,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.
Skills Required
- BS/MS in Electrical Engineering or Computer Science or equivalent experience
- 3-5+ years of relevant experience
- Strong understanding of VLSI digital design, layout, and timing closure
- Basic knowledge of circuit design, device delays, and gate-level timing
- Familiarity with EDA tools: Cadence Innovus/Quantus/Tempus, Synopsys Fusion Compiler/ICC2/StarRC/PrimeTime, Mentor Calibre
- Proficient programming/scripting: Perl, Python, Tcl, C-shell, make
- Experience with hardware description languages: Verilog, VHDL
- Solid understanding of hierarchical physical design strategies and advanced-node technology issues
- Hands-on STA experience including multi-mode multi-corner analysis and timing closure
- Self-motivated team worker with good verbal and written interpersonal skills
- Experience with Cadence Innovus/Genus/Conformal and Synopsys PrimeTime/StarRC (added advantage)
- Proven track record of tape-out quality GDSII and silicon success in sub-10nm (plus)
What We Do
Ambarella (Nasdaq: AMBA) is a leading developer of visual AI products. Our technologies enable a wide variety of human and computer vision applications, including video security, advanced driver assistance systems (ADAS), electronic mirror, drive recorder, driver/cabin monitoring, autonomous driving, and robotic applications. Ambarella’s low-power system on chips (SoCs) offer high-resolution video compression, advanced image processing, and powerful deep neural network processing to enable intelligent cameras to extract valuable data from high-resolution video streams. For more information, please visit www.ambarella.com
