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Develop and debug verification testbenches, tests, RTL logic, random test generators, coverage monitors, checkers, assertions, and simulation-analysis tools for complex SoCs featuring DSP, computer vision, CPU, and coprocessor blocks.

Design and verify ASIC logic for edge AI vision processors, including video compression, image processing, neural-network accelerators, and processor cores. Develop RTL in Verilog and SystemVerilog, optimize designs for timing, area, and power, and create UVM-based testbenches, BFMs, test generators, coverage monitors, and verification plans. Support synthesis, front-end tool flows, chip bring-up, and testing.

Implements and verifies design-for-test features, including scan, compression, MBIST, LBIST, and streaming scan networks, for complex computer vision SoCs. Develops scan and memory-test patterns, analyzes clocking for at-speed testing, performs post-layout timing verification, supports ATE pattern bring-up, and assists with silicon production, failure diagnosis, and test optimization.

Design, train, optimize, and validate deep learning and computer vision algorithms for edge devices. Implement and optimize models for runtime on Ambarella hardware and assess performance on large-scale datasets.

Develop, bring up, and verify embedded platforms and drivers in C/C++ on ARM/MIPS. Work with RT-Linux, lab equipment, and hardware teams to implement and test low-level control drivers and ensure system-level integration.

Design and verify video-compression, image-processing, vector-compute, and edge AI processor subsystems using SystemVerilog/Verilog. Synthesize and optimize RTL for timing, area, and power; prototype microarchitectures with scripting; develop unit tests, front-end flows, and coverage analysis; participate in chip bring-up and testing.

Develop and optimize low-level software, microcode, and runtimes to deploy AI workloads on Ambarella AI SoCs. Improve tooling, SDKs, profiling and debugging infrastructure, collaborate with architecture/hardware/compiler teams, and support customers integrating and optimizing models for edge AI performance.

Lead go-to-market strategy for Ambarella's AI vision processors across AIoT markets. Define product (hardware/software), drive partner ecosystem, coordinate with engineering and sales, gather customer requirements, and organize tradeshows and webinars to grow new and existing markets.

Lead product marketing for next-generation edge AI and IoT silicon. Define market opportunities, product requirements, roadmaps, and go-to-market plans; drive cross-functional development, launches, lifecycle management, stakeholder relationships, and product performance analysis.

Optimize, quantize, prune and deploy computer-vision deep learning models (PyTorch) onto Ambarella SoC/CVflow. Train and validate models, profile performance on target hardware, implement optimizations, build preprocessing and inference tooling, troubleshoot the model garden, and create tutorials. Collaborate using C/C++ and Python and follow modern software development practices.