Top Tech Jobs & Startup Jobs

Design, develop, test, and update computer hardware and embedded systems. Create schematics and prototypes, perform analog/mixed‑signal and power supply design, run lab testing, ensure EMC/EMI compliance, and support manufacturing handoff and validation.

Senior design verification engineer responsible for system-level verification using SystemVerilog/UVM and C/C++ testbenches. Duties include testplan development, building BFM/driver/monitor/scoreboard components, stress and corner testing, failure debug, assertions, coverage closure, gate-level simulations, and customer reporting.

Support warehouse design and operational excellence by designing layouts, specifying material handling equipment, leading capital projects and optimization initiatives, documenting standards, analyzing performance, and supporting automation and vendor coordination to improve safety, productivity, and service levels across distribution centers.

Design and execute SystemVerilog/UVM verification environments: plan verification, write constrained-random and directed tests, measure and close coverage, run gate-level sims, and automate regressions. Work includes C-based processor-in-loop tests, emulation, memory/MMU and DSP/memory-subsystem verification, and power-aware/formal methodologies when applicable.

Design and develop hardware from concept through production for microcontroller-based systems. Create analog and mixed-signal circuits, power supplies, and manage signal integrity. Use EDA tools for schematic/PCB design, validate prototypes with lab equipment, ensure EMI/EMC compliance (automotive), and collaborate with firmware, mechanical, and test teams to ensure manufacturability and robustness.

Responsible for DFT implementation for 3nm/5nm networking SoCs and IPs: RTL checks, scan insertion, ATPG (compressed/uncompressed), pattern simulation, MBIST and JTAG insertion/verification, silicon debug/bring-up, automation and scripting (Perl/Shell/TCL), and low-power DFT work.

Lead architecture and implementation of SoC design verification environments using SV/UVM. Develop constrained-random, self-checking testbenches, SoC test firmware in C/C++, automate verification flows, close coverage/regression, and support multi-million gate ASIC tapeout including formal verification and methodology improvements.

Designs and delivers workplace AI (Microsoft 365 Copilot) and Power Platform enablement: discovery, workshops, prototypes/POCs, reusable templates, governance alignment, training, and adoption programs to transition solutions to end-user teams.

Execute synthesis, place-and-route (PnR), and static timing analysis (STA) for ASIC partitions, drive signoff (LEC, physical verification, EM/IR), collaborate with architects/RTL/DFT teams, refine physical design methodologies, troubleshoot flows and work with EDA vendors, and meet tight schedules and low-power design targets.

Lead test engineering for embedded hardware and software: design and run test plans, automate frameworks, track and resolve defects, perform root-cause analysis, mentor team members, and collaborate with cross-functional teams to improve product quality.