Top Tech Jobs & Startup Jobs

Design-for-test (DFT) lead for 3nm/5nm networking SoCs: implement scan insertion, ATPG (compressed/uncompressed), MBIST and JTAG insertion/verification, run RTL checks, pattern simulation and silicon bring-up; debug mismatches and automate/optimize DFT flow using scripts and Makefile enhancements.

Design and verify FPGA/RTL using Verilog/SystemVerilog, develop scripts, and use EDA tools for simulation, linting, CDC, low-power (UPF) and timing signoff. Work with PCIe and AMBA interfaces, ARM fabric IP, IP-XACT, and report progress to customers. Onsite work at client locations (San Jose or Austin).

Sell Arrows interconnect, passive and electromechanical product line to existing accounts in a defined territory. Build and maintain customer and supplier relationships, provide quotations, close business, plan territory/accounts, and support value-added and supply-chain engagements.

Manage accounting and financial functions for a multi-million dollar business unit: review reconciliations, oversee GL staff, research complex GAAP issues, deliver financial analysis and forecasting, maintain controls, train staff, escalate risks, and support month/quarter/year-end close processes.

Design-for-test (DFT) implementation and validation for 3nm/5nm networking SoCs and IPs. Perform RTL checks, scan-insertion, ATPG pattern generation (compressed/uncompressed), pattern simulation, MBIST and JTAG insertion/verification, silicon debug, and automation/scripting to enhance DFT flows.

Design, develop, test, and update computer hardware and embedded systems. Create schematics and prototypes, perform analog/mixed‑signal and power supply design, run lab testing, ensure EMC/EMI compliance, and support manufacturing handoff and validation.

Drive regional demand creation and revenue growth for Altera FPGAs by identifying target accounts, influencing early design decisions, aligning field and supplier sales teams, managing top opportunities, and communicating pipeline status. Collaborate with FAEs, FSRs, and Altera sales to close technical and commercial barriers and execute regional growth strategies.

Senior design verification engineer responsible for system-level verification using SystemVerilog/UVM and C/C++ testbenches. Duties include testplan development, building BFM/driver/monitor/scoreboard components, stress and corner testing, failure debug, assertions, coverage closure, gate-level simulations, and customer reporting.

Manage assigned accounts for Southern Ohio, drive solution selling and margin growth, qualify leads, process excess inventory, collaborate with Arrow teams, and maintain account data and reviews.

Support warehouse design and operational excellence by designing layouts, specifying material handling equipment, leading capital projects and optimization initiatives, documenting standards, analyzing performance, and supporting automation and vendor coordination to improve safety, productivity, and service levels across distribution centers.