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Develop and support Cadence Innovus physical implementation and routing software. Responsibilities include enhancing data models, place-and-route flows, databases, performance, APIs, and class definitions; troubleshooting and debugging software; and supporting P&R design workflows. The role requires strong software engineering expertise, IC design data-model knowledge, database architecture experience, and efficient data-access algorithm skills.

Designs analog integrated circuits at Cadence. The provided description contains no further responsibilities, qualifications, or project details beyond the role title and compensation information.

Leads the PLM configuration team and manages product lifecycle data, BOM configurations, component compliance, change control, supply readiness, system integrations, environmental governance, and ISO 9001 procedures. Oversees PLM process improvements, cross-functional collaboration, departmental OKRs, budgeting, reporting, and team development. The role requires extensive configuration management and PLM leadership experience, systems administration expertise, regulatory training, and proficiency with multiple PLM, supply chain, and productivity tools.

Develops high-speed wireline communications transceivers through numerical modeling and architecture. Selects and specifies transceiver components, evaluates end-to-end system tradeoffs, collaborates with analog and digital designers, and supports laboratory characterization of completed designs. The role requires advanced mathematical modeling, communication systems, signal processing, coding, data analysis, signal propagation, circuit knowledge, and experimental skills. The position is based full-time in San Jose.

Manage and improve sales compensation plans, incentive funds, goal letters, MBOs, quota credit, payout estimates, commissions accruals, and related data processes. Analyze large datasets, create reports and recommendations, audit results, resolve issues, and collaborate with sales, finance, IT, and operations teams. Lead cross-functional process improvement initiatives while meeting schedules, budgets, and quality standards.

Lead functional verification for Cadence memory controller IP. Develop and enhance UVM-based verification environments, create test plans, validate customer configurations through regression testing, analyze functional and code coverage, support customers using the environment, and ensure designs meet technical and quality requirements.

Develop and enhance Cadence’s Xcelium RTL/logic simulator and timing-constraint verification technology. Design and optimize graph algorithms for massive SDC constraint graphs, perform C/C++ performance tuning, reduce compilation time and memory usage, write specifications and unit tests, and collaborate with globally distributed engineering teams.

Architect and enhance Cadence’s Xcelium RTL/logic simulator and timing constraints verification technology. Design scalable graph algorithms for multi-billion-node graphs, optimize C/C++ performance and memory usage, develop specifications and unit tests, lead junior engineers, and collaborate with global teams on semiconductor verification software.

Develop compiler software for Cadence’s Palladium emulation platform. Responsibilities include solving large-scale compilation challenges involving logic optimization, partitioning, scheduling, multithreading, and distributed computing. The role requires strong data structures and algorithms knowledge, proficiency in C/C++, debugging skills, Linux/Unix development experience, and familiarity with hardware description languages and electronic design platforms.

Develop compiler software for the Cadence Palladium hardware emulation platform. Responsibilities include solving large-scale compilation challenges involving logic optimization, partitioning, routing, multithreading, and distributed computing. The role requires strong C/C++ programming, data structures and algorithms knowledge, debugging, Linux/Unix development, and familiarity with hardware description languages and electronic design platforms.