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The role involves physical layout design for mixed-signal circuits in CMOS technologies, collaborating with multi-disciplinary teams, and utilizing Cadence tools for various layout tasks.

Lead technical customer engagement for NVIDIA's AI and Autonomous Vehicles products, collaborating on architecture and developing technical solutions while managing partner relationships and resource development.

Lead full-flow physical implementation for LPU ASICs: synthesis, floorplanning, place & route, timing closure, UPF/LEC low-power flows, and tapeout. Collaborate with IP, front-end, PnR and sign-off teams to optimize PPA and resolve bottlenecks. Architect automated, data-driven EDA methodologies, implement scripts and AI-assisted optimizations, and ensure sign-off quality including power grid, EMIR, and DFT integration for high-speed SerDes blocks.

Responsible for analyzing architectural requirements, delivering high-performance RTL blocks, collaborating with engineers, and assisting in IP solution integration.

Develop and maintain end-to-end deployment workflows for Warp-based robotics on embedded platforms (e.g., Jetson). Optimize on-device performance, debug across Python/C++/CUDA/ drivers, integrate with ROS 2/Isaac stacks, and build testing and CI/packaging infrastructure for embedded targets.

Design and implement high-speed SerDes (80Gbps+) from transistor-level architecture through layout, verification, and silicon characterization. Optimize circuits for noise, power, and loop stability in FinFET/deep-submicron CMOS nodes. Collaborate with layout on floorplanning and high-speed routing. Lead post-silicon bring-up, debugging, modeling, and top-level verification of analog and digital blocks.

The role involves developing network firmware features, collaborating on design, implementing features, and debugging firmware issues.

Lead customer-facing support for networking hardware, firmware, and software in supercomputer and AI fabric projects. Diagnose and resolve complex system issues, liaise with R&D and marketing, and influence product requirements while driving visible customer engagements.

Lead cross-functional programs to operationalize and optimize end-to-end service fulfillment and logistics (order intake, kitting, shipping, returns, repairs). Manage 3PL/4PL/warehousing/carrier relationships, define performance benchmarks and dashboards, drive continuous improvement (Lean/Six Sigma), and lead change management for WMS/TMS/FSM/ERP integrations to ensure SLA and on-time delivery performance worldwide.

As a Senior SOC Design Engineer, you will integrate IP blocks, develop methodologies, streamline SOC design, and ensure high-quality RTL delivery.