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Lead federal Physical AI partner ecosystem growth by advising partners, driving integrations of NVIDIA technologies, enabling go-to-market assets, onboarding startups, mapping partner opportunities, and collaborating cross-functionally to influence product roadmaps and accelerate strategic deals.

Manage a team developing accelerated image and data compression libraries. Define project goals, roadmap, and scope; ensure execution and delivery; elevate engineering practices; collaborate with internal and external customers and the open-source community while fostering an inclusive, innovative environment.

Lead product strategy and roadmaps for inference tools, SDKs, and libraries that enable developers to deploy and optimize GenAI models on NVIDIA GPUs. Partner with internal and external developers, engineering, leadership, and marketing to prioritize features, drive product delivery, and define go-to-market plans focused on performance, cost, and safety.

Lead development and production of new products through NPI, perform wafer sorting and yield analysis, support failure analysis with the foundry, create technical documentation and test plans, and build PDE methodologies to ensure manufacturing quality and performance.

This role involves researching and optimizing applications for NVIDIA's computing platform, collaborating with customers and internal teams to enhance performance and design next-generation software and hardware.

Lead and scale an engineering team building GPU-accelerated deep learning inference frameworks. Drive strategy and roadmap, partner with compiler/libraries/research teams, oversee performance tuning and multi-GPU optimizations, mentor engineers, and deliver production-ready inference pipelines for LLM, multimodal, and generative AI across datacenter and edge platforms.

Design and optimize CUDA kernels and cluster-scale distributed systems for deep learning. Prototype system and compiler optimizations, profile hardware-software interactions, collaborate with researchers and architects, and deliver high-performance runtime tools and maintainable code for training and inference at scale.

Lead development and optimization of verification infrastructure and test suites for Ethernet switch SDKs. Collaborate with hardware, firmware, DevOps, and software teams to build CI/CD pipelines, dashboards, benchmarks, and automation for pre/post-silicon validation. Guide architecture, coordinate global verification projects, and mentor junior engineers.

Design, develop, and optimize system software and firmware for SoC-based O-RAN infrastructure. Implement power-management policies (DVFS, clock/power gating, thermal control), analyze RU/DU workloads, build performance and power models, create measurement and test tooling, validate on simulation/emulation and silicon, and influence SoC and platform architectures for 5G/6G deployments.

Lead DFT methodology and IP design for SoC products, owning fuse controller architecture, RTL development, verification, and full-chip test plans. Collaborate with cross-functional teams for integration, support post-silicon bring-up and ATE validation, debug failures, and mentor junior engineers.