Top Tech Jobs & Startup Jobs

Design and build scalable automation, testing, and infrastructure for NVIDIA deep learning libraries across platforms. Develop full-stack tools from UIs to cluster and database layers, configure CI/CD, and advance industry-standard tooling to improve build, test, integration, and release workflows.

The Lead Design Engineer will create and manage innovative designs for automotive harnesses and setups, collaborating with vendors and leading projects to meet engineering build expectations.

Design, build, and deliver scalable SAP IBP planning solutions (response & supply, demand). Support and enhance planning processes, prototypes, integrations, dashboards, and end-to-end material, supply, replenishment, deployment, and service-parts planning to improve profitability and operational performance.

Lead failure analysis and debug of datacenter DGX/MGX/HGX systems during mass production. Diagnose HW/SW/FW issues across boards, systems, and racks, run experiments, collect/analyze data, enable DFx, provide root-cause and corrective actions, write reports and debug guides, and coordinate with vendors, factories, and partner teams worldwide.

Lead product engineering for datacenter GPU systems through production ramp: define test specs, ensure DFx and signal integrity, optimize assembly and test flow, drive component qualifications and BOM updates, analyze volume data to resolve yield/test issues, and support customer escalations to meet cost, quality and throughput targets.

Lead technical engagements enabling advanced AI infrastructure and integrations. Provide architecture direction, prototype and validate solutions, own strategic programs, develop reference architectures, and share field learnings to inform product and engineering.

The role focuses on optimizing communication performance for deep learning systems, designing protocols, and collaborating on hardware/software integration while exploring innovative technologies.

You will deliver and verify Networking features, develop verification infrastructure, automate tests, and enhance product quality.

Design and implement algorithms and tools for chip-level placement, reshaping, and global routing. Develop computational geometry, placement, routing and graph-optimization solutions, apply machine learning for design space exploration, extend GUIs for debugging/visualization, and collaborate with design teams to deploy high-performance C++ tools impacting next-generation AI chip physical layouts.

Verify digital design, golden models and micro-architecture of SerDes IPs using UVM/VMM and SystemVerilog. Build BFMs, monitors, checkers and scoreboards, define verification scope and infrastructure, write test plans, execute coverage-driven and assertion-based verification, and collaborate with architects, designers and pre/post-silicon teams to ensure product-quality delivery on compressed schedules.