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The role involves owning physics models, defining manufacturing specifications, and validating designs to ensure product quality and performance. The architect will utilize first-principles thinking and AI to improve workflows and drive alignment across engineering teams.

The role involves co-designing system-level speed features, validating silicon behavior, and leading debug processes, focusing on speed and reliability in silicon engineering.

Define, build, and validate low-power features for NVIDIA's next-generation AI products, focusing on scalable workflows, telemetry analytics, and automated validation.

Provide expert-level technical support for NVIDIA DGX compute/GPU platforms: triage and resolve hardware and software issues on multi-distro Linux, debug installations and interoperability, coordinate with engineering/marketing, create KB articles, and improve support processes. Interact directly with customers via phone/email/conference and apply AI tools for debugging and documentation.

Lead design and optimization of next-generation high-speed IOs (NVLink, NVLink-C2C), focusing on IO power management, power/performance modeling, interoperability, and deep debug across cross-functional teams to enable product bringup and release.

Lead validation of ML datacenter stacks from cluster to rack scale for CSPs: define test strategies, reproduce and triage customer bugs, validate fixes, run perf benchmarks, manage test data and tooling, produce release-readiness reports, and collaborate with internal and partner engineering teams.

Lead and coordinate global DGX Cloud infrastructure programs, gather requirements, drive roadmaps and schedules, manage risks and issues, improve development workflows, and communicate status across engineering, product, and cloud provider partners.

Architect and deliver voltage-noise mitigation across silicon, package, board, and platform. Define product noise targets, build Sim-to-Si correlation, model and prototype transient/noise features, lead bringup bug resolution, and drive cross-functional co-design tradeoffs to ship robust PDN solutions.

The Senior DFT Engineer will design testing methodologies, work with cross-functional teams, mentor junior engineers, and enhance test access mechanisms and validation processes for complex semiconductor chips.

Lead development and optimization of semi-custom RTL-to-GDS methodologies, collaborate with internal/external IP vendors, drive PPA and floorplan experiments, ensure IP integration and handoffs, improve methodology/tool flows from synthesis through timing and layout, and support customer-focused SOC/IP development and quality assurance.