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The role involves designing diagnostic software for NVIDIA's systems, collaborating with teams to ensure software integration, and evaluating technical standards for product lifecycle phases.

Responsible for analyzing architectural requirements, delivering high-performance RTL blocks, collaborating with engineers, and assisting in IP solution integration.

Design, develop, and verify features for next-gen RISC-V controllers on NVIDIA GPUs, collaborate with hardware and software teams, perform early modeling/simulation, follow devices through development to customer products, and support BSP and device driver development.

As a Senior Firmware Engineer, you will design, implement, and maintain firmware, optimize code paths, and collaborate with various teams to integrate systems and resolve issues in complex hardware interactions.

Drive innovation in DFT engineering by developing test methodologies, collaborating with vendors, and mentoring junior engineers in silicon test strategies.

The role involves driving timing analysis and closure for NVIDIA's hardware, collaborating with cross-functional teams, and contributing to advanced technology projects.

The role involves developing AI applications for VLSI design using machine learning and related technologies. Duties include infrastructure design, AI solution implementation, collaboration with teams, and maintaining design databases.

The Senior I/O Subsystem Architect will design and define chip-to-chip communication standards, leading projects from concept to deployment while collaborating with various teams to develop interconnect technology.

Design and develop server applications for managing NVLink networks, collaborate on new features, and oversee integration testing and QA.

Lead SoC-level verification as the primary Person-in-Charge: own verification plans, schedules, and sign-off from conception through tape-out. Coordinate across architects, IP owners, emulation/FPGA teams, and infrastructure; track status and risks, drive mitigation plans, and evolve SoC verification flows and methodologies to achieve coverage and tape-out criteria.