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Design and prototype hardware systems and PCBs; build mechanical housings; develop hardware control software and applications; perform lab testing and characterization (oscilloscope, power and SI measurements); use 3D modeling and 3D printing for prototypes; soldering and scripting for test automation; analyze results and guide integration toward production.

Lead failure analysis and debug of datacenter DGX/MGX/HGX systems during mass production. Diagnose HW/SW/FW issues across boards, systems, and racks, run experiments, collect/analyze data, enable DFx, provide root-cause and corrective actions, write reports and debug guides, and coordinate with vendors, factories, and partner teams worldwide.

Design and build end-to-end Real2Sim pipelines and neural 3D reconstruction systems that convert multi-sensor data into simulation-ready scene and object assets. Integrate outputs with mapping, localization, and multi-sensor fusion, collaborate with ML researchers, deploy and optimize large-scale data-generation and augmentation pipelines, and validate and monitor production reconstruction and simulation services.

Lead NVIDIAs global analyst relations strategy and market intelligence organization. Shape research agendas, market narratives, TAM/SAM models, and early-warning insights. Advise executives, align cross-functional teams, and grow the AR and Market Intelligence teams to influence product strategy and long-range planning.

Design and implement an LLVM-based backend JIT compiler for NVIDIA GPUs. Develop compiler passes and optimizations, focusing on high performance and low compile time. Collaborate with hardware, compiler, and application teams to resolve issues and influence future GPU architectures.

Lead architecture, deployment, and operation of a hybrid HPC–quantum platform. Manage Linux-based GPU clusters, QPU hardware, schedulers (Slurm), networking, storage, and vendor integrations. Enable researchers by optimizing, benchmarking, and documenting hybrid workflows and supporting application performance and orchestration across classical and quantum systems.

Design, develop, test and maintain data-forwarding and offload features for Ethernet switches and SmartNICs. Implement routing, ACLs, QoS, NAT, VxLAN-EVPN and other network functions, collaborate with architects, QA and support, and lead multi-functional teams on large feature development and delivery.

Lead development and adoption of Warp by implementing CUDA C++ and Python integrations, turning CUDA features into supported functionality, integrating CUDA-X libraries, partnering with internal teams for production integration, and designing APIs and abstractions to expand simulation, optimization, and AI workloads.

The Senior Software Performance Engineer will optimize NVIDIA's autonomous driving solutions, enhance software architecture efficiency, and develop performance-driven product code in C++, collaborating with multiple teams.

Lead development and improvement of ASIC integration, build, simulation, CI, and debug infrastructure for high-speed IO GPU IP. Apply automation, metrics, and AI-assisted workflows to improve reliability, turnaround, and debuggability. Collaborate across design, verification, firmware, methodology, and infrastructure teams to root-cause failures and deliver durable process improvements.