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Leads semiconductor DFX innovation programs from architecture and methodology development through silicon validation, field deployment, and productization. Coordinates engineering, software, manufacturing, datacenter, and field operations teams; manages schedules, dependencies, scope, risks, technical reviews, and executive communication. Drives process improvement, automation, and standardized program execution across complex, ambiguous chip development initiatives.

Research and develop GPU-acceleration techniques for high-performance databases, ETL, and data analytics applications. Analyze data-intensive workloads, optimize algorithms, memory management, and CUDA kernels, and investigate CPU/GPU bottlenecks. Collaborate with research, hardware, software, and industry teams to influence next-generation architectures, programming models, and data-processing solutions.

Designs and delivers AI-augmented enterprise integration platforms, API ecosystems, and autonomous workflows. Responsibilities include developing event-driven distributed systems, integrating SAP and SaaS applications, managing API lifecycles, supporting EDI deployments, implementing secure identity and access controls, and building CI/CD and observability capabilities. The role uses agentic AI, workflow automation, and intelligent monitoring to enable self-healing, adaptive integration across cloud and enterprise environments.

Develop and verify bare-metal firmware for NVLINK-C2C, supporting pre-silicon validation, silicon bring-up, feature enablement, and hardware/firmware debugging. Build automation and AI-assisted verification flows, investigate boot and training failures, correlate firmware execution with RTL behavior, and collaborate with software, RTL, design verification, emulation, and post-silicon teams. Lead interface validation strategy and contribute to chip bring-up activities.

Develop and deploy internal ASIC design tools, RTL generation workflows, verification utilities, and methodologies across NVIDIA engineering teams. Maintain DevOps-style automated RTL generation operations, support reusable design blocks, and integrate workflows into IP development environments. Requires digital design and Verilog expertise, Python or Perl scripting, Unix/Linux shell scripting, and Makefiles. Experience with ASIC verification, clocks/resets, CDC flows, synthesis, and timing is advantageous.

Leads NVIDIA’s semiconductor ecosystem account strategy, partner relationships, and global go-to-market execution. Develops sales strategies, enables partners and field teams, drives pipeline and revenue, closes complex deals, and provides customer feedback to product teams. The role requires deep AI/ML and conversational AI expertise, executive relationship management, solution strategy, sales leadership, event engagement, and up to 50% global travel.

Design, develop, test, and extend NVIDIA’s large-scale object storage platform. Responsibilities include improving availability, reliability, durability, fault tolerance, and performance across deployments exceeding 10,000 nodes and exabytes of data. The role also automates storage infrastructure provisioning, management, and monitoring; supports AI/ML research teams; owns product delivery through support; and contributes to open-source storage projects.

Leads Software Engineering Productivity and Release Engineering for Cumulus Linux. Manages teams supporting build infrastructure, package repositories, developer environments, CI pipelines, code analysis, and engineering productivity tooling. Oversees infrastructure monitoring, troubleshooting, Linux build systems, release processes, and scalable automation while partnering with development, testing, IT, and DevOps teams.

Architect and maintain profiling frameworks for CPU and GPU environments, benchmark EDA applications, analyze memory and kernel performance, identify bottlenecks, optimize memory usage, and develop predictive models for hardware procurement and cloud instance selection.

The Senior DFT Engineer will design testing methodologies, work with cross-functional teams, mentor junior engineers, and enhance test access mechanisms and validation processes for complex semiconductor chips.