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The Gateway Site Development Engineer at SpaceX will design antenna sites, create infrastructure plans internationally, and ensure performance for the Starlink network. This role involves problem-solving, project management, and collaboration across teams to drive the development of global antenna sites and improve system health.

As a Sr. Gateway Site Development Engineer, you will be responsible for designing antenna sites, creating development plans with international partners, and ensuring successful global antenna roll-outs for Starlink. This role includes managing complex projects and engaging with cross-functional teams for optimal system performance.

As a Sr. Data Analyst for the Starlink Payments team, you will define and develop payment metrics, analyze data for insights to improve conversion rates and costs, prepare presentations with findings, support new market launches, and collaborate with various teams to ensure data accuracy.

The Automation & Controls Engineer will design and implement automated solutions for SpaceX's Starship production line. Responsibilities include developing control systems, wiring panels, PLC programming, and managing projects to ensure completion within budget and timeline.

Launch Operations Engineers at SpaceX are responsible for the operational processes during launch events, including developing test requirements, analyzing performance data, and providing engineering support on console. They work closely with hardware testing and optimization for the entire launch system while ensuring safety protocols are followed.

The Wireless Modem Design Verification Engineer will be responsible for verifying digital ASIC and FPGA designs, writing test plans, developing test harnesses, and executing testing processes. This includes automating test case generation with Python and MATLAB, contributing to pre-silicon verification alongside cross-disciplinary teams, and ensuring the reliability of designs for SpaceX's Starlink network.

As an ASIC/FPGA Verification Engineer at SpaceX, you will be responsible for digital ASIC and FPGA verification, writing and reviewing test plans, and developing testbench infrastructure using SystemVerilog. Your role includes automating test cases with Python and MATLAB, and contributing to both pre-silicon and post-silicon validation of designs.