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As a Senior Physical Design Engineer, you will be responsible for high speed physical designs, including floorplanning and physical verification for block and chip-level designs. You will work on congestion resolution, timing closure, and interface with various teams while using tools like Innovus and Calibre. Full chip tapeout experience with 3nm technologies is preferred.

The R&D Engineer Physical Design will focus on ASIC implementation, engaging in various tasks such as synthesis, floorplanning, and ensuring timing closure. The role requires collaboration across teams for quality assurance and design validation, leveraging expertise in EDA tools to adapt to evolving project requirements.

The R&D Engineer will manage projects from concept to high-volume manufacturing, focusing on integrated-circuit technologies and semiconductor assembly. Responsibilities include defining process flows, conducting design reviews, and supporting yield analysis and design robustness in advanced semiconductor designs.

The Product Line Manager will be involved in defining product roadmaps for High-Speed Optical Communication and managing relationships with partners and customers. Responsibilities include overseeing product lifecycle, managing marketing strategies, and writing product requirements documents.

The Principal Physical Design Engineer will oversee high-speed physical designs, including floorplanning, physical implementation, verification, and timing closure. The role requires collaborating with multiple teams to ensure effective design methodologies and confronting challenges such as timing closure and congestion resolution. Strong problem-solving skills and proficiency with design tools are necessary.

As a Principal Engineer, you will undertake the design and development of Ethernet NIC product features, collaborating with cross-functional teams to ensure the delivery of high-performing software and firmware components while engaging with QA to define testing protocols and addressing customer issues.

The IC Design Engineer will define architectural specifications, perform RTL design utilizing Verilog HDL, implement low-power designs, and collaborate with teams for verification and physical design processes. Responsibilities include debugging, timing closure analysis, and system-level validation on FPGA/emulation.