Top Tech Jobs & Startup Jobs

The role involves triaging and resolving complex issues with Fibre Channel HBAs, collaborating on product releases, and creating technical documentation to aid customer implementation.

Own and evolve an enterprise COBOL application used for test data generation and demo environments. Lead roadmap, write and deploy COBOL code, integrate with mainframe subsystems (Db2, IMS, CICS, IDMS, Datacom), support CI/CD and DevOps tooling, advise internal teams, and establish governance for contributions.

Senior mainframe technical consultant delivering Broadcom mainframe software adoption: presentations, demos, installations, configurations, deployments and POCs. Architect solutions with sales teams, provide technical leadership during trials, document requirements, and build customer relationships. Travel-intensive role supporting multi-country accounts and meeting financial and internal process targets.

Design and optimize mechanical aspects of ASIC packages using FEA. Collaborate with teams, conduct validations, and document designs across multiple projects.

Perform system-level signal and power integrity design, simulation, measurement and debug for high-speed SerDes systems (up to 400G). Collaborate with package, PCB, and silicon teams, develop EM and circuit models, perform VNA/TDR and oscilloscope measurements, correlate measurement-simulation, define SI/PI requirements, and support customer deliverables and documentation.

Lead technical project execution for 20+ concurrent package/PCB designs focusing on high-speed SerDes and high-power delivery. Manage and develop engineers, coordinate customers/vendors, create SI/PI methodologies, support package/PCB technologies, oversee lab measurements and correlations, and drive automation and project management practices.

Execute full-chip physical design from RTL to tape-out, including synthesis, place-and-route, timing closure (top-level STA), clock tree synthesis, EM/IR analysis, floorplanning, physical verification, flow/methodology development, and collaboration with RTL designers. On-site work required in Colorado Springs.

Design and deliver high-quality SystemVerilog RTL for advanced-node SoCs (5nm and below). Optimize PPA, perform CDC/RDC analysis and low-power design, drive timing closure and physical-design handoff, and collaborate with Architecture, Verification, and Physical Design teams. Work spans specification through tapeout readiness.

Perform static timing analysis and timing closure for high-performance SoC ASICs. Work with logic and physical design teams to debug constraints, create timing ECOs, implement timing infrastructure, analyze critical timing paths, and develop scripts/methodologies. Document guidelines and communicate issues through to resolution.

Perform full-chip physical IC design from RTL to tape-out including synthesis, place-and-route, STA/timing closure, EM/IR analysis, clock tree synthesis, floorplanning, and physical verification while collaborating with RTL designers and developing flows/methodologies.