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Forecast and track government incentives, grants, and related funding across multiple regions. Develop cash flow forecasts, working inventory forecasts, financial models, variance analyses, and executive reporting. Support planning cycles, financial close, audits, compliance documentation, and management presentations. Collaborate with finance, accounting, operations, and leadership teams to improve forecasting accuracy and reporting efficiency for major semiconductor manufacturing investments.

The NPI Integrator will lead new product/process introduction, coordinating documentation, tracking processes, and ensuring product compliance through development cycles.

As a Senior Formal Verification Engineer, you will develop verification strategies and environments for AI SoCs, ensuring the correctness of digital designs through formal verification methods and collaboration with engineering teams.

Define and own adapter/IPU/DPU/NIC card and platform architectures, driving integration across SoC, board, firmware, OEMs and data center requirements. Specify manageability, thermal/power, reliability, and serviceability; lead cross-functional reviews and deliver actionable architecture artifacts and roadmaps.

The Lead Analog SerDes Architect will define circuit architecture for optical interconnects, leading design work, collaborating with teams, and guiding junior engineers.

Own and sustain diffusion/implant toolsets in a 300mm high-volume fab. Ensure tool matching, MOR availability, safety and cleanliness. Lead tool installations, qualifications, process development, experiments, and continuous-improvement roadmaps to drive yield, availability, cycle time, and low defectivity. Train production engineers and support technology transfers; may serve as on-shift engineer.

Design and execute verification plans and UVM-based testbenches to validate CPU logic and microarchitecture. Run system-level simulations, debug pre-silicon issues, collaborate with architects and RTL designers, maintain verification infrastructure, and document strategies to ensure functional, performance, and power goals are met.

Design, configure, and develop SAP MDM/MDG and S/4 HANA solutions. Gather business and system requirements, create specifications, implement customizations, automate workflows, and perform testing. Troubleshoot production issues, lead small subsystems/projects, collaborate with stakeholders, and support large-scale SAP MDM and S/4 HANA migration programs.

Lead architecture and design of next-generation high-speed I/O PHYs and analog/mixed-signal circuits (TX/RX) in advanced process nodes. Define floorplans, simulate analog behavior, verify against microarchitecture, optimize PPA and yield, collaborate with layout and architecture teams, provide technical leadership, mentor engineers, and drive designs to market.

Develop and optimize thin-film metal deposition processes for advanced semiconductor technologies, including high-k/metal gate, contacts, and interconnects. Responsibilities include experimental design, process data analysis, materials characterization, equipment qualification, yield improvement, manufacturability, and silicon validation. The engineer collaborates with integration, device, metrology, manufacturing, and equipment teams while supporting next-generation process pathfinding and on-call manufacturing operations.