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The role involves leading a global sales team, developing custom ASIC sales strategies, managing long-cycle sales processes, and building executive relationships with clients to drive revenue growth for Intel's custom silicon solutions.

Lead enterprise-scale yield and defect engineering programs in high-volume semiconductor manufacturing. Define multi-year strategy, integrate AI/ML and automation, drive defect metrology and inspection systems, improve yield and cycle time, and build a high-performing multidisciplinary organization to operationalize predictive decision intelligence across sites.

Provide high-level administrative and operational support to two senior leaders: manage complex calendars, travel, meetings, logistics, onboarding, SharePoint and departmental operations, triage requests, and support events while maintaining confidentiality and process improvements.

Lead development of device collateral, design rules, and test-chip structures for advanced CMOS nodes. Drive scribe-line layouts, DRC/physical verification, DOE and SPC-based data analysis, and cross-functional alignment to optimize yield and device performance in high-volume manufacturing.

Drive defect identification and reduction for advanced silicon process technologies using metrology tools (SEM/TEM), data analysis, and cross-functional collaboration. Create defect-reduction roadmaps, qualify process fixes, support ramp-to-manufacturing, present defect summaries, and partner with yield, integration, and failure analysis teams.

Drive factory availability and output by identifying supplier-related module issues, leading data-driven root cause analysis (8D/FMEA/SPC), coordinating with OEM suppliers, establishing control standards, closing MQIs, and enabling supplier personnel and cost/performance improvements across factory operations.

Develop and qualify manufacturable semiconductor process modules: define roadmaps, flows, equipment and materials; plan experiments and statistical characterization; drive yield, quality, reliability, and productivity improvements; establish process control and sustain through volume ramp; support technology transfer, factory start-up, training, and on-shift engineering for toolset needs.

Perform functional verification of GPU graphics logic (3D, media, display); develop scalable IP verification plans, testbenches, and coverage-driven environments; run simulations, root-cause and debug presilicon issues; collaborate with architects, RTL and physical design teams; document test plans and improve verification infrastructure and methodology.

Design and execute verification plans for mixed-signal IP using OVM/UVM and SystemVerilog/Verilog. Build testbenches and analog behavioral models, run system-level simulations, debug presilicon issues, collaborate with architects/RTL/physical design teams, and document verification results while contributing to reusable verification infrastructure.

Lead enterprise programs to transform yield and defect engineering using AI, digital twins, and automation. Define strategy, drive defect metrology and scalable yield systems, resolve complex yield limiters, and build a high-performing cross-disciplinary team to improve ramp, cycle time, and productivity across high-volume semiconductor manufacturing.