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Develop and optimize RF and analog test solutions from feasibility through production. Design test boards, perform ATE and bench characterization, debug functionality and performance, correlate ATE-to-DV, tune thermal and power recipes, and develop software to drive advanced test equipment to ensure product quality and yield.

Design and optimize CPU logic and RTL, write and simulate RTL for CPU IP blocks, meet PPA and timing goals, ensure physical design integrity, review verification plans, document microarchitectural specs, and collaborate with SoC customers for integration.

The Module Development Engineer will optimize semiconductor manufacturing processes, develop defect inspection tools, and collaborate with suppliers to advance technology.

The Software Engineer will design, develop, and maintain cloud-native applications and distributed systems, manage infrastructure, and support operations with an emphasis on security and automation.

Seek a Senior CPU Power Management Architect for creating and ensuring optimal performance in CPU designs, focusing on power management architecture, collaboration across teams, and post-silicon debugging.

The role involves leading wet etch and cleans development, focusing on advanced logic process integration and mentoring engineers.

Lead substrate supplier development and qualification, manage readiness milestones, collaborate with engineering teams, and ensure supplier capabilities meet customer demands.

The CEG Technical Assistant/Chief of Staff supports CEG's strategic initiatives, managing executive operations, stakeholder relationships, and driving business objectives. Responsibilities include collaboration across Intel, facilitating communication amongst teams, and enhancing organizational processes.

Designs and oversees development of Intel GPU AI software across the entire stack, ensuring performance, stability, and ease of use, while mentoring technical leaders and aligning technical strategies with organizational goals.

Lead block-level physical design for qubit control ASICs: drive RTL-to-GDS convergence via synthesis and PnR, perform floorplanning, timing/power/IR analysis, physical verification, ECO and sign-off, co-optimize IP and libraries, and develop PD methodologies to meet aggressive PPA and yield targets.