Top Tech Jobs & Startup Jobs

Develop and validate compact transistor models (FinFET, GAA) and simulation methodologies for PDKs. Collaborate cross-functionally to ensure modeling readiness, perform statistical, RF and EM simulations, automate analysis with Python, and integrate innovative techniques like OMI and ML to meet delivery milestones.

Lead CMP module development and deployment across advanced nodes, drive process optimization, defect reduction, and yield improvement. Own CMP technical direction, collaborate cross-functionally and with suppliers, mentor engineers, and ensure manufacturing readiness, process control, and metrology alignment to support product execution and customer success.

Lead physical design timing efforts for next-generation SoCs: perform timing analysis and optimization, generate and validate timing constraints, define PVT conditions, develop timing models and flows, collaborate with clocking, architecture, and logic teams to ensure high-performance, low-power chip integration.

Drive custom ASIC and silicon sales across the Americas: define regional GTM strategy, build executive relationships, manage long-cycle technical deals, shape solutions with internal partners, develop pipeline and forecasts, influence roadmaps, and close high-value custom silicon opportunities.

Perform hands-on lab failure analysis and electrical fault isolation for packaged semiconductor assemblies, develop and apply characterization techniques, recommend corrective actions, collaborate across teams to improve yield, and support program milestones on a required on-site shift schedule.

Perform hands-on failure analysis and root-cause determination for assembled package yield loss and in-line failures. Conduct electrical fault isolation, defect characterization, data acquisition and analysis, and recommend corrective actions. Develop failure analysis techniques and best practices, collaborate across teams and customers, and support program milestones. Lab-based role requiring on-site shift work and clear communication of findings to yield and integration stakeholders.

The DFT Application Engineer will provide technical support on DFT methodologies, drive quality improvements, and develop documentation for customers, ensuring successful ASIC tape-outs.

The Software Applications Development Engineer will create full stack integrated software solutions, manage project lifecycles, and enhance business efficiency for Intel's NPI Tools team.

The CPU Performance Architect at Intel will design CPU logic, optimize performance and power, and collaborate with engineering teams on innovative microarchitectures for advanced computing products.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.