EDA Tools Hardware Engineer

Reposted 24 Days Ago
Be an Early Applicant
4 Locations
In-Office
142K-269K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.
Summary Generated by Built In
Job Details:

Job Description: 

The Role and Impact
Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. As part of Intel, you will have the unique opportunity to collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.
Key Responsibilities

  • Full Chip Implementation Flow Development

  • Develop and maintain full-chip physical implementation flows including:

  • Floor planning and partitioning strategies

  • Hierarchical block integration

  • Chip-level placement and routing coordination

  • Power grid planning and analysis

  • Clock tree synthesis (CTS) strategy integration

  • Enable scalable SoC assembly flows for multi-block and multi-power domain designs.

  • Define methodology for hierarchical design reuse and integration

Qualifications:

Minimum Qualifications

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master's degree with 4+ years of experience; or a PhD with 2+ years of experience

  • Physical design fundamentals (I.e. placement, routing)

  • Clock tree synthesis (CTS)

  • Full-chip integration methodologies using Innovus

Preferred Qualifications

  • Static timing analysis (STA)

  • Power grid design and IR drop concepts

  • Experience with large SoC or multi-block design implementation flows

  • Experience scripting and automation skills in Linux environments

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

Business group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field with 6+ years; or Master's with 4+ years; or PhD with 2+ years
  • Physical design fundamentals (placement, routing)
  • Clock tree synthesis (CTS)
  • Full-chip integration methodologies using Innovus
  • Static timing analysis (STA)
  • Power grid design and IR drop concepts
  • Experience with large SoC or multi-block design implementation flows
  • Scripting and automation skills in Linux environments

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

Intel Insights

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.

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