The Role and Impact
As a Staff Device Modeling Engineer, you will play a pivotal role in advancing circuit simulation and modeling capabilities for next-generation semiconductor technologies. Your daily responsibilities will include collaborating with cross-functional teams to drive the development of high-quality simulation tools and methodologies, ensuring alignment with technology roadmaps, and enabling optimized solutions for process design kits (PDKs). Your contributions will directly impact accelerating product delivery timelines and enhancing Intel's leadership in the foundry space.
Business Group
You will be joining Intel's Design Technology Platform (DTP) organization, a critical pillar that empowers Intel Foundry customers to produce cutting-edge products for the marketplace. The Compact Device Modeling Group (CDMG), within DTP, focuses on co-optimizing Intel's state-of-the-art process technology and design tools to enable the development of innovative, high-performance products. As part of this team, you will contribute to the modeling solutions that allow design teams to deliver leadership products for data-centric applications faster and with greater precision.
Key Responsibilities
- Partner with technology leaders and PDK teams to ensure modeling capabilities align with roadmap requirements.
- Drive readiness and validation of simulation and modeling solutions to meet PDK delivery milestones.
- Develop compact device models (e.g., FinFET, GAA) for transistor modeling, including layout-dependent effects and circuit performance impacts.
- Conduct statistical modeling, simulation, and data analysis using Python scripting and other relevant tools.
- Implement innovative methodologies for device targeting benchmarking circuits, self-heating effects, and Open Model Interface (OMI) modeling.
- Collaborate across multiple teams and geographies to achieve seamless integration and optimized solutions.
- Bachelor's degree in Electrical Engineering or a related discipline with 6+ years of industry experience in the semiconductor field; -OR- Master's degree in Electrical Engineering or a related discipline with 4+ years of relevant industry experience; -OR- Ph.D. in Electrical Engineering or a related discipline with 2+ years of experience.
- 2+ years of hands-on experience with compact modeling techniques for advanced nodes such as FinFET and GAAFET.
- Proficiency with commercial simulators (e.g., HSPICE, Spectre) and extraction tools (e.g., ICCAP, MBP).
- Experience in Python scripting for data analysis and automation.
- Experience in statistical modeling, RF simulation, and EM simulation.
Preferred Qualifications
- Ph.D. in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field.
- Strong background in Device physics and RF modeling.
- Experience in RF structure design, RF De-embedding and EM simulation.
- Experience collaborating across teams and geographies, with experience leading technical initiatives.
- Experience with machine learning algorithms and their application in compact model development.
- Strong understanding of process flows, circuit design, and simulation methodologies.
Join us in shaping the future of semiconductor technology innovation. Take the next step in your career by applying today and becoming part of a team dedicated to driving impactful solutions for Intel Foundry customers worldwide.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Electrical Engineering or related discipline with 6+ years industry experience OR Master's with 4+ years OR Ph.D. with 2+ years
- 2+ years hands-on experience with compact modeling techniques for advanced nodes (FinFET, GAAFET)
- Proficiency with commercial simulators (e.g., HSPICE, Spectre) and extraction tools (e.g., ICCAP, MBP)
- Experience in Python scripting for data analysis and automation
- Experience in statistical modeling, RF simulation, and EM simulation
- Ph.D. in Electrical Engineering or related discipline with 3+ years industry experience
- Strong background in device physics and RF modeling
- Experience in RF structure design, RF de-embedding and EM simulation
- Experience leading technical initiatives and collaborating across teams and geographies
- Experience with machine learning algorithms applied to compact model development
- Strong understanding of process flows, circuit design, and simulation methodologies
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
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