Top Tech Jobs & Startup Jobs

Design and develop RTL logic for SoC blocks, integrate IP and subsystems, optimize for power/performance/area/timing, ensure quality for physical implementation, apply secure hardware development practices, and collaborate with IP providers to validate SoC designs.

Drive yield improvement for leading-edge logic process nodes by analyzing fab, defect, and electrical data; build statistical and ML models to identify root causes; develop measurement recipes and tools; collaborate with design and factory teams to enable manufacturability and new product introductions; document procedures and support production debugging.

Develop and validate test programs for wafer sort, unit class, burn-in and parametric testing. Define test plans, debug results, coordinate with design, yield, foundry, and test operations, and improve tester/tool performance.

Directs and manages design verification engineers for Subsystem and SoC design, enhances verification processes, and ensures security compliance while leading team performance.

Lead Intel's U.S. government affairs strategy, advising executives, managing lobbying staff and consultants, shaping policy advocacy across federal and state governments, ensuring compliance with lobbying disclosures, building relationships with policymakers and agencies, and representing Intel in industry and government forums.

Design and implement DFT features (SCAN, MBIST, BSCAN) via RTL (Verilog/VHDL/SystemVerilog); provide timing closure and test content for manufacturing; collaborate across architecture, design, verification, and manufacturing; develop HVM/ATE content; verify post-silicon features; optimize power, performance, area, timing, and test coverage to meet DPM goals.

Design, simulate, validate, and optimize silicon photonic integrated circuits across the chip lifecycle. Lead tape-outs, collaborate with foundries and cross-functional teams, enable high-volume manufacturing, perform reliability and statistical analysis, and develop test plans and documentation to deliver known-good-die photonic solutions.

Lead global network operations to ensure resilient, highly available network services across manufacturing sites, labs, offices, campuses, and data centers. Own incident, problem, change, and service management; drive automation, observability, and AI-enabled operations; manage monitoring, capacity, vendor SLAs, and disaster recovery. Mentor global teams, coordinate with architecture, engineering, and cybersecurity, and communicate operational health and major incident responses to senior leadership.

Design, develop, and optimize oneCCL communication library features for low-latency, high-throughput HPC workloads. Collaborate with scientists and hardware teams on Aurora supercomputer integrations, implement and enhance communication protocols, benchmark and analyze performance across configurations, and debug complex cross-layer hardware/software issues.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.