- Develop logic designs and RTL code for SoC blocks and subsystems aligned with architectural and microarchitectural specifications
- Integrate IP blocks and subsystems into comprehensive full-chip SoC designs
- Participate in the definition of architecture and microarchitecture features of the blocks being designed
- Optimize logic designs to meet power, performance, area, and timing goals using advanced tools and strategies
- Conduct quality checks to ensure design integrity and readiness for physical implementation
- Review verification plans to confirm accuracy in tested design features and implement corrective measures for failing RTL tests
- Apply secure development practices to address security models and objectives in hardware design
- Collaborate with IP providers to integrate and validate IPs at the SoC level
- Ensure quality assurance compliance for smooth IP/SoC handoff and design readiness
- Collaborative Communicator — Proven ability to work across teams and convey complex technical ideas clearly and effectively
- Innovative Thinker — Enthusiasm for staying ahead of industry trends and applying creative approaches to SoC design challenges
- Execution-Driven — Demonstrated success in delivering complex projects from concept through implementation
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field with 4+ years of hands-on experience in logic design, RTL development, and microarchitecture implementation, or Master's degree with 3+ years of experience in the same fields
- The years of experience must include:
- RTL coding languages such as Verilog
- Expertise in SoC integration, SoC clocking, and low-power design methodologies
- Experience in strategies for timing, power convergence, and physical implementation optimization
- Hands-on experience with Clock Domain Crossing techniques and Network-on-Chip (NoC) architectures
- Working experience with AMBA protocols such as CHI, AXI, AHB, and APB
- Hands-on experience from spec to timing closure in at least one SoC/ASIC design
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 4+ years experience, or Master's degree with 3+ years experience
- RTL coding experience (e.g., Verilog)
- Expertise in SoC integration, SoC clocking, and low-power design methodologies
- Experience in timing, power convergence, and physical implementation optimization strategies
- Hands-on experience with Clock Domain Crossing techniques and Network-on-Chip (NoC) architectures
- Working experience with AMBA protocols (CHI, AXI, AHB, APB)
- Hands-on experience from spec to timing closure in at least one SoC/ASIC design
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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