Top Tech Jobs & Startup Jobs

The CPU Performance Architect will define CPU architectures, model performance, analyze bottlenecks, collaborate on designs, and resolve microarchitecture issues to enhance CPU efficiency.

Lead and define end-to-end SoC functional verification strategies (simulation, emulation, formal), drive verification closure for high-speed interfaces and integrated IPs, establish reusable UVM-based methodologies, oversee emulation/prototyping, debug pre-silicon issues, mentor engineering leads, and collaborate across architecture, RTL, firmware, and post-silicon teams to ensure first-pass silicon success.

Design and develop custom SRAMs and digital circuits for Intel CPUs. Optimize memory performance and work with domain experts on innovative technologies.

As a Semiconductor Device Modeling Engineer at Intel, you will support modeling activities for new semiconductor technologies using tools and simulations to enhance design efficiency.

Support installation, maintenance, and automation of design and compute environments for Intel PDKs and EDA tools. Troubleshoot designer issues to TapeOut, integrate new tools and workflows, collaborate with PDK, flow, product, and compute teams, provide training/documentation, and interact with EDA vendors to ensure required features and quality.

As a Compiler Engineer at Intel, you will design, develop, and maintain their LLVM-based compiler stack, collaborate with hardware teams, and enhance performance through optimizations and debugging.

Design, implement, and optimize CPU microcode features. Collaborate with architects and design engineers to integrate microcode, perform performance analysis, debug RTL, and identify improvements for processor performance and reliability.

Serve as an SAP MM/PP business systems analyst: gather requirements, design and configure SAP MM/PP solutions, plan and execute testing, troubleshoot production issues, lead small subsystems or features, and manage small-to-medium projects while collaborating with SMEs and stakeholders.

Lead end-to-end strategic foundry customer programs, acting as primary customer interface and coordinating cross-functional teams (engineering, supply chain, manufacturing, finance) to drive execution from engagement through production ramp and EOL. Manage risks, capacity planning, demand forecasting, escalations, governance, and continuous improvement to meet schedule, cost, and quality commitments.

Lead RTL design and microarchitecture for SoC IP blocks, implement and integrate Verilog/SystemVerilog RTL, collaborate with verification and physical design teams for timing/power closure, drive silicon bring-up and post-silicon validation, mentor junior engineers, and ensure secure development and quality assurance for SoC/ASIC projects.