The New Mexico Silicon Manufacturing (NM Si Mfg) Yield Department is seeking Process Integration and Defect Reduction Engineers to support backend interconnect and advanced packaging semiconductor fabrication. These roles support Fab 11X, with a focus on Intel's Foveros and EMIB technologies.
In this position, you will partner with teams across Yield Engineering, including Process Integration, Defect Reduction, Quality and Reliability, Device Analysis, and Yield Analysis. You will be responsible for sustaining process health as products transition from development into high-volume manufacturing (HVM) while driving improvements in yield, quality, reliability, cost, and manufacturability.
The NM Si Mfg Yield team is looking for engineers who are passionate about problem-solving, data analysis, and cross-functional collaboration. You will design and execute experiments, analyze process and yield data, and optimize manufacturing processes to reduce defects and improve overall product performance. Responsibilities include managing technology change introductions, monitoring inline defectivity and parametric performance, investigating process excursions, identifying root causes, and implementing corrective actions. In addition, you will support the transfer of new products from Technology Development (TD) into manufacturing and ensure readiness for successful high-volume production.
Desired Skills and Behavioral Traits
The ideal candidate will demonstrate:
- Strong teamwork, leadership, problem-solving, and prioritization skills in a high-performance environment.
- Excellent written and verbal communication skills.
- The ability to present technical information clearly and effectively to audiences with varying levels of technical expertise.
- The ability to work independently with minimal supervision while effectively managing multiple priorities.
- Experience leading factory-level projects and delivering results in a timely manner.
- Strong project management skills, with the ability to execute roadmaps that drive improvements in yield, defect reduction, efficiency, and cost.
- The ability to balance collaboration and critical thinking to drive data-based decisions and technical solutions.
Minimum Qualifications
- Bachelor's or Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Materials Science, Microelectronics Engineering, Chemistry, Physics, or a related technical field.
- 3+ years of experience in the semiconductor industry.
This position is not eligible for Intel immigration sponsorship.
Preferred Qualifications
- 3+ years of experience in process integration or defect reduction for backend interconnect or advanced packaging processes.
- 3+ years of experience applying Design of Experiments (DOE) methodologies.
- 3+ years of experience in data analysis and statistical process control using tools such as JMP, SQL, PCS, or similar platforms.
- Strong understanding of semiconductor manufacturing process flow and advanced packaging technologies.
- Knowledge of process capability, specification limits, statistical variation, and process control methodologies.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, New Mexico, AlbuquerqueAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $120,860.00-170,630.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's or Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Materials Science, Microelectronics Engineering, Chemistry, Physics, or a related technical field
- 3 or more years of experience in the semiconductor industry
- 3 or more years of experience in process integration or defect reduction for backend interconnect or advanced packaging processes
- 3 or more years of experience applying Design of Experiments methodologies
- 3 or more years of experience in data analysis and statistical process control using JMP, SQL, PCS, or similar platforms
- Strong understanding of semiconductor manufacturing process flow and advanced packaging technologies
- Knowledge of process capability, specification limits, statistical variation, and process control methodologies
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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