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Lead device development and characterization for next-generation DRAM, drive electrical data analysis and root-cause for yield improvement, support node introductions and fab ramps, coordinate cross-functional technical solutions, and mentor engineers to advance device performance and product quality.

As a Product Architect, you will analyze DRAM system architectures, identify bottlenecks, lead innovations, define memory features, and mentor junior engineers.

As a Yield Technology Equipment Engineer, you will create inspection techniques, monitor tool maintenance, track process control, and collaborate with engineering and vendors.

The role involves developing metrology applications, optimizing measurements, collaborating with vendors, and implementing solutions in a semiconductor manufacturing environment.

As a Materials Planning Engineer, you will manage forecasts for spares and materials, improve manufacturing efficiencies, and collaborate across teams to ensure optimal material availability and budgeting compliance.

The role involves defining advanced package architectures, conducting trade-off studies, building models, running simulations, and providing architectural direction for memory systems.

The Principal Node Development Product Engineer drives product readiness by collaborating with various teams, analyzing silicon data, and addressing integration risks in DRAM technology development.

The Thin Films Engineer develops deposition processes for EUV-enabled DRAM, focusing on process optimization and defect reduction while collaborating with multifunctional teams.

Design block-level layouts using Cadence Virtuoso including floorplanning, placement, routing, and optimization. Apply physical constraints (PDN, pin placement, routing blockages), ensure DRC/LVS/density/reliability compliance, support parasitic extraction, post-layout verification, ECOs, and create partial custom layouts for device-level or small analog blocks while collaborating with cross-site teams.

Develop and optimize advanced packaging photolithography processes (including thick resist patterning), drive yield and defect reduction using DOE/SPC/FMEA, diagnose lithography issues via failure analysis, lead equipment/material evaluations and support technology transfer to high-volume manufacturing through cross-functional collaboration.