Top Tech Jobs & Startup Jobs

Lead physical design implementation and signoff for advanced DRAM digital designs from RTL to tapeout. Drive timing closure, power integrity (PDN/IR drop/EMIR), EM verification, and reliability. Collaborate across architecture, RTL, implementation, CAD, and tech teams to resolve timing, congestion, and signal integrity issues, deploy methodology and automation, mentor engineers, and influence physical design roadmaps.

Design and deliver RTL for complex DRAM digital and mixed-signal blocks. Perform front-end quality checks (linting, CDC/RDC), develop SDC constraints, run synthesis and STA, drive timing closure, and optimize power, performance, and area. Collaborate with architecture, verification, and physical design teams and improve RTL-to-GDS flows and automation.

Lead verification of HBM and DRAM IP, subsystem, and full-chip designs using coverage-driven methodologies. Develop verification plans, UVM testbenches, automated regressions, and debug complex issues. Drive verification closure, mentor engineers, and improve verification automation including AI-assisted flows while collaborating with cross-functional teams.

Identify enterprise AI opportunities, evaluate emerging models and platforms, build prototypes and proofs-of-concept, quantify business value, and present recommendations to technical and executive stakeholders to drive AI adoption across the company.

Design and deliver RTL for complex DRAM digital and mixed-signal blocks; perform front-end quality checks (lint, CDC/RDC), synthesis, timing constraint development (SDC), STA, power optimization (UPF), and collaborate with architecture, verification, and physical design to meet PPA targets and improve RTL-to-GDS flows.

Lead enterprise data loss prevention and information protection programs: design and tune DLP policies, develop advanced IP detection (regex, fingerprints, ML), implement classification/labeling and rights management, automate remediation and workflows, monitor exfiltration/anomalous access, author standards and runbooks, and drive large-scale security initiatives across endpoints, cloud, email, SaaS, and storage.

The Staff/Principal Engineer will support material quality, filtration strategy, and risk mitigation initiatives globally, collaborating with teams to align technical requirements and improve manufacturing performance.

Lead tapeout execution and release coordination for HBM designs, manage schedules, ensure compliance with release prerequisites, and track closure of signoff items before tapeout.

Ensure validation, product development, and process learnings are propagated across DRAM technologies. Collaborate with DRAM technology pillars to prioritize cross-portfolio lesson sharing, drive data collection and analysis for Best-Known Method coverage, consolidate and document alignment activities, and work with manufacturing DFT/Test Development and Silicon Strategy teams to implement cross-technology and design-based alignment.

The Equipment Engineer will oversee and optimize CMP equipment, while the Process Engineer will enhance manufacturing processes, focusing on DRAM development and SPC initiatives.