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The Staff Physical Design Engineer will manage the full physical design flow for a high-speed interface chip, ensuring timing closure, power integrity, and tape-out quality. Responsibilities include defining floorplans, executing place and route, resolving DRC/LVS/ERC issues, and collaborating closely with teams.

As a Low Power Architect, lead the definition and modeling of SoC-level power architecture for HBM logic die and memory-centric SoCs, focusing on delivering performance-per-watt solutions. Responsibilities include collaborating with various teams to drive power management strategies and ensuring efficient implementation of power intents.

Build and scale cell characterization infrastructure for standard and custom cells across process nodes. Develop automated MCMM flows, Liberty model generation and validation, integrate flows with design/verification/CAD teams, root-cause SPICE/STA/silicon mismatches, and enable characterization for HBM, DRAM, TSV, and high-speed interfaces.

Develop and optimize advanced packaging photolithography processes (including thick resist patterning), drive yield and defect reduction using DOE/SPC/FMEA, diagnose lithography issues via failure analysis, lead equipment/material evaluations and support technology transfer to high-volume manufacturing through cross-functional collaboration.

The HBM SoC Physical Design Engineer will implement advanced HBM SoC designs, optimize performance and power, and collaborate with various teams to ensure robust physical design integrity.

The Staff CAD Engineer role involves developing Physical Verification tools and methodologies for memory designs, collaborating with various teams to enhance product development strategies.

Own and execute a global strategic account plan for a major OEM. Build senior-level customer relationships and a global relationship map. Manage multi-product opportunity pipeline with accurate forecasting and CRM discipline. Deliver quarterly revenue, margin, and TAM share targets. Identify and develop new strategic sales opportunities and influence cross-functional teams. Leverage AI tools to enhance account strategy and execution.

Manage the lifecycle of High Bandwidth Memory (HBM) products, driving development across teams, schedule management, and communication of progress and priorities.

The role involves leading Dry Etch process development for DRAM, mentoring engineers, collaborating across teams, and defining technical roadmaps to enhance yield and manufacturability.

Lead startup, development, and optimization of wet etch processes for DRAM production. Improve yield, reduce cost, resolve manufacturing issues, collaborate with equipment and integration teams, and drive SPC-based process improvements while meeting project milestones.