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Support development of advanced process technology through CAD, scripting, and automation tools for product development and physical design.

Lead a team in developing next-generation vertically stacked DRAM while optimizing process flows and collaborating on technical issues. Conduct experiments and analyze data to enhance performance and manufacturability.

This role involves optimizing manufacturing processes through data analysis and tool application while ensuring safety compliance and mentoring staff.

Lead the integration of new layered memory technologies, focusing on semiconductor device architecture and performance optimization. Collaborate with teams to improve yield and drive multi-functional projects, applying extensive knowledge in device physics and engineering.

Lead integration and productization of new layered memory devices by developing device architectures, optimizing process flows, designing and executing R&D fab experiments, analyzing defect/parametric data, and driving cross-functional teams to meet performance and reliability targets.

Design and implement high-performance Verilog/SystemVerilog RTL for HBM digital blocks. Define micro-architecture, optimize area/power/performance, address CDC/RDC and timing, apply low-power methodologies (CPF/UPF, clock gating), support synthesis/STA/SDC, collaborate with verification/DFT/physical design, and assist post-silicon debug and verification closure.

The EUV Lithography Pathfinding Engineer will evaluate advanced lithography technologies, lead pathfinding activities, collaborate on roadmap requirements, and ensure implementation readiness for new patterning approaches.

The Photolithography Process Engineer supports lithography operations, monitors tool health, executes control plans and assists in process improvements.

Design, build, test, deploy, and operate AI-first full stack applications and custom agents using MCP, LLMs, RAG, and cloud-native platforms. Own features end-to-end, integrate AI services, harden systems for reliability, and apply AI-assisted development practices.

Lead a team executing wet process, CMP, and wafer bonding development for DRAM. Oversee 24/7 shift operations, wafer movement, data quality, process monitoring, and line recovery. Mentor engineers, improve workflows and AI adoption, and drive cross-functional collaboration to accelerate technology delivery.