Top Tech Jobs & Startup Jobs

Own the power architecture for Physical AI SoCs, including power domains, DVFS, power states, power delivery, and low-power techniques. Define on-die power management, PMIC interfaces, sensors, telemetry, and hardware/software controls. Establish energy and thermal budgets, model PPA trade-offs, integrate UPF-based power intent, and validate designs through silicon bring-up. Partner across silicon, firmware, thermal, package, and software teams while setting methodology standards and mentoring engineers.

Designs and evaluates AI model architectures for efficient hardware implementation. The role analyzes transformers and other models, translates computation graphs into hardware dataflows, develops performance and efficiency models, and collaborates across machine learning, software, and hardware teams. Responsibilities include optimizing models for specialized platforms and identifying opportunities for hardware-software co-design in cloud, edge, robotics, autonomous systems, and Physical AI.

Design and implement SoC power-management hardware, including digital power meters, activity monitors, throttlers, thermal control loops, clock and reset architecture, DVFS, power domains, retention, and low-power flows. Correlate power estimates across RTL, emulation, and silicon, and develop telemetry for power and thermal behavior. Collaborate with architecture, physical design, package, firmware, software, and verification teams.

Own and scale emulation infrastructure for a next-generation Physical AI SoC. Responsibilities include emulator bring-up, flow optimization, regression automation, HW/SW co-verification, pre-silicon software validation, waveform debugging, performance analysis, and FPGA prototyping. The role partners across architecture, RTL, verification, software, and systems teams to validate complex SoC designs and real-world workloads.

Leads financial strategy, planning, budgeting, forecasting, accounting operations, reporting, audits, tax compliance, cash flow, treasury, and capital allocation. Oversees a small finance team, improves financial systems and processes, supports growth initiatives and potential M&A, and provides financial insights to company leadership. Requires extensive high-tech startup finance experience and strong knowledge of GAAP, technical accounting, and financial modeling.

Owns end-to-end execution of a semiconductor SoC program from architecture through tapeout, silicon bring-up, and production readiness. Coordinates silicon, hardware, software, third-party IP vendors, foundries, OSATs, and manufacturing partners. Maintains integrated schedules, manages risks and dependencies, leads milestone reviews and executive reporting, drives decisions, and establishes program management processes for a growing engineering organization.

Verify Velaura’s next-generation Physical AI SoC from RTL blocks through complete HW/SW systems. Responsibilities include developing SystemVerilog and UVM environments, assertions, coverage, formal verification, emulation, FPGA prototyping, performance and safety validation, post-silicon debug, and root-cause analysis. The role covers compute engines, memory, interconnects, processors, DMA, firmware, drivers, and operating-system interactions while collaborating across architecture, RTL, software, and systems teams.

Lead architecture and development of an AI accelerator compiler stack, including model ingestion, graph lowering, optimization, quantization, code generation, partitioning, diagnostics, and verification. Partner with hardware, firmware, runtime, and model teams to optimize executable artifacts for NPUs. Lead hiring, mentoring, and technical direction for compiler and ML systems engineers.

Leads DFT architecture, methodology, implementation, verification, sign-off, silicon bring-up, and production ramp for complex AI and high-performance ASIC/SoC designs. Oversees scan, ATPG, MBIST, LBIST, JTAG, fault simulation, coverage closure, memory repair, timing, and test-mode integration. Partners across RTL, verification, physical design, STA, validation, manufacturing, and product engineering. Drives DFT tools and automation, post-silicon diagnosis, yield improvement, quality metrics, and team leadership.

Own functional verification of custom CPU units from test planning through coverage closure. Build SystemVerilog and UVM environments with C/C++, stimulus, checkers, assertions, and coverage. Verify instruction execution, caches, memory ordering, coherence, exceptions, privilege behavior, performance, and reliability. Run regressions, support emulation and FPGA prototyping, enable pre-silicon software bring-up, and perform hardware-software root cause analysis.