- Responsibilities
● Lead architecture and development of the AI accelerator compiler stack.
● Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, TensorFlow Lite, or similar.
● Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.
● Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.
● Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.
● Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.
● Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.
● Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.
● Establish compiler verification and regression strategy for graph transformations,IR lowering, numerical behavior, model accuracy, and performance.
● Hire, mentor, and lead a team of compiler and ML systems engineers.
● Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.
● Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces.
● Strong C++ and Python programming skills and experience building production-quality compiler or systems software.
● Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.
● Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.
● Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and SQA.
● Experience leading technical teams or major architecture areas.
- Preferred Qualifications
● Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.
● Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.
● Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA,TorchDynamo/TorchInductor, or other model import flows.
● Familiarity with robotics, computer vision, CNNs, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads.
● Experience building customer-facing compiler diagnostics and model-porting tools.
● Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.
● Open-source compiler contributions or experience working with external framework communities.
Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.
Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.
Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.
Skills Required
- Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems
- Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces
- Strong C++ and Python programming skills
- Experience building production-quality compiler or systems software
- Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, or OpenVINO-like systems
- Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering
- Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and SQA
- Experience leading technical teams or major architecture areas
- Experience with NPU, GPU, DSP, or AI accelerator compiler stacks
- Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling
- Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA, TorchDynamo/TorchInductor, or other model import flows
- Familiarity with robotics, computer vision, CNNs, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads
- Experience building customer-facing compiler diagnostics and model-porting tools
- Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts
- Open-source compiler contributions or experience working with external framework communities
What We Do
Velaura AI develops ultra-low-power silicon and software for AI compute infrastructure, serving cloud, edge, and physical-AI applications. Its patented, energy-efficient digital-design technology and power-optimized architectures support next-generation AI accelerators, helping compute systems scale with lower energy use. Drawing on deep semiconductor expertise, the company aims to make AI computing more efficient across data centers and intelligent devices, with performance and sustainability central to its approach.
