Top Tech Jobs & Startup Jobs

Own the architecture and technical direction of a heterogeneous AI SoC runtime spanning sensor ingest, preprocessing, inference, postprocessing, and application delivery. Define execution, memory, synchronization, driver, firmware, compiler-runtime, observability, resilience, and validation architectures. Lead cross-functional engineers while contributing hands-on to production systems software, performance optimization, APIs, and low-level interfaces for robotics and edge AI workloads.

Own verification of custom AI accelerator hardware, including matrix and vector engines. Develop SystemVerilog and UVM environments, reference models, assertions, checkers, coverage, and regressions. Verify numerical precision, quantization, data flow, performance, latency, and power efficiency across RTL blocks and complete systems. Collaborate with architecture, software, compiler, runtime, and systems teams through design bring-up, emulation, and pre-silicon validation.

Own the CAD and engineering infrastructure supporting silicon development, including compute, storage, scheduling, cloud, security, disaster recovery, EDA tools, licensing, and RTL-to-GDS flow releases. Lead CI/CD, regression infrastructure, flow qualification, vendor strategy, and AI-assisted engineering adoption. Ensure scalable, reproducible, secure platforms support concurrent SoC programs and thousands of weekly jobs while partnering with RTL, verification, DFT, physical design, packaging, and software teams.

Serves as the first point of contact for the office while managing reception, visitors, mail, packages, conference rooms, supplies, vendors, invoices, workplace inventory, interviews, events, onboarding, and general administrative support. The role requires strong organization, communication, discretion, and proficiency with office productivity, calendar, collaboration, and video-conferencing tools.

Leads the architecture and development of customer-facing SDKs, APIs, CLI tools, examples, documentation, developer workflows, and portal integrations for an AI SoC platform. Partners across AI, multimedia, robotics, tools, release, and SQA teams to deliver reliable installation, deployment, compatibility, and release experiences. The role also hires, mentors, and leads engineers focused on developer tools, documentation systems, APIs, and sample applications.

Develop system-level performance models and simulation frameworks for AI workloads, software runtimes, and hardware architectures. Model SoC components, memory systems, and interconnects; analyze bottlenecks and architectural tradeoffs; and evaluate latency, throughput, scalability, and energy efficiency. Collaborate with hardware architects, software engineers, and ML teams to support hardware-software co-design and guide next-generation AI compute platform decisions.

Design and verify Velaura’s next-generation Physical AI SoC from RTL blocks through full hardware and software systems. Responsibilities include building SoC simulation environments, verifying boot, root of trust, clock/reset, low-power, IO and memory subsystems, running CDC/RDC analysis, evaluating performance and QoS, and supporting coverage closure, signoff, and tape-out. The role also involves hardware-software co-verification, emulation, FPGA prototyping, and post-silicon debugging.

Design and optimize RTL for a high-speed, low-power SoC memory subsystem, including memory controllers, PHY integration, DFI interfaces, training, calibration, power management, scheduling, ECC, and performance optimization. Collaborate with architecture, software, verification, physical design, IP, and PHY teams through silicon bring-up. The role requires deep expertise in Verilog/SystemVerilog, memory technologies, computer architecture, and low-power digital design.

Design and optimize RTL for key portions of a high-performance, power-efficient SoC. Collaborate with architects, software, verification, and physical design teams on microarchitecture, hardware/software interfaces, memory systems, interconnects, compute engines, DMA, and power-management logic. Analyze performance, power, and area tradeoffs, resolve bottlenecks, and contribute to production silicon development for Physical AI applications.

Lead architecture, transistor-level design, optimization, and verification of high-performance, low-power standard cells and custom digital circuits for advanced AI and HPC silicon. Own PPA optimization, arithmetic circuit development, statistical and reliability verification, layout collaboration, characterization, ASIC sign-off, methodology improvements, and silicon readiness. Mentor engineers and provide technical leadership across circuit design and advanced semiconductor development.