Top Tech Jobs & Startup Jobs

The RTL Design Tech Lead will manage RTL design for ASIC/SoC projects, lead a team of engineers, ensure high design quality, and drive projects from architecture to tapeout.

Write and develop a ~5-minute 3D animated short and supporting content: brainstorm, outline, script, character briefs, set descriptions, social media sketches, and collaborate with creative leadership and storyboard artists through pre-production to deliver a polished script for animation.

Lead the architecture definition for advanced semiconductor products, focusing on SoC design, performance modeling, and cross-functional collaboration in a tech lead role.

The CPU Compiler Lead will optimize code for a high-performance RISC-V CPU, manage integration of language standards, and lead compiler optimization efforts.

Lead the development of a high-performance compiler stack for GPU architecture, focusing on optimization passes, collaboration with hardware architects, and team coordination.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

Lead end-to-end hardware architecture for next-generation GPU compute platforms, define high-speed PCB topologies and PDNs, optimize PCIe/serdes fabrics, coordinate SI/PI and thermal co-design, and lead technical engagement with JDM/ODM partners through bring-up, failure analysis, and HVM transition.